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数据转换器
模数转换器 (ADC)
高速 ADC (≥10MSPS)

ADS61B29

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12 位、250MSPS 模数转换器 (ADC)

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ADS61B29

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产品详情

Sample rate (max) (Msps) 250 Resolution (Bits) 12 Number of input channels 1 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 700 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 790 Architecture Pipeline SNR (dB) 70.1 ENOB (Bits) 11.1 SFDR (dB) 92 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 250 Resolution (Bits) 12 Number of input channels 1 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 700 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 790 Architecture Pipeline SNR (dB) 70.1 ENOB (Bits) 11.1 SFDR (dB) 92 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFN (RGZ) 48 49 mm² 7 x 7
  • Integrated High Impedance Analog Input Buffer
  • Maximum Sample Rate: 250 MSPS
  • 14-Bit Resolution — ADS61B49
  • 12-Bit Resolution — ADS61B29
  • 790 mW Total Power Dissipation at 250 MSPS
  • Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
  • Programmable Fine Gain up to 6 dB for SNR/SFDR Trade-Off and 1-Vpp Full-Scale Operation
  • DC Offset Correction
  • Supports Input Clock Amplitude Down to 400 mVPP Differential
  • 48-QFN Package (7mm × 7mm)
  • Pin Compatible with ADS6149 Family
  • APPLICATIONS
    • Multicarrier, Wide Bandwidth Communications
    • Wireless Multi-Carrier Communications Infrastructure
    • Software Defined Radio
    • Power Amplifier Linearization Feedback ADC
    • 802.16d/e
    • Test and Measurement Instrumentation
    • High Definition Video
    • Medical Imaging
    • Radar Systems
  • Integrated High Impedance Analog Input Buffer
  • Maximum Sample Rate: 250 MSPS
  • 14-Bit Resolution — ADS61B49
  • 12-Bit Resolution — ADS61B29
  • 790 mW Total Power Dissipation at 250 MSPS
  • Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
  • Programmable Fine Gain up to 6 dB for SNR/SFDR Trade-Off and 1-Vpp Full-Scale Operation
  • DC Offset Correction
  • Supports Input Clock Amplitude Down to 400 mVPP Differential
  • 48-QFN Package (7mm × 7mm)
  • Pin Compatible with ADS6149 Family
  • APPLICATIONS
    • Multicarrier, Wide Bandwidth Communications
    • Wireless Multi-Carrier Communications Infrastructure
    • Software Defined Radio
    • Power Amplifier Linearization Feedback ADC
    • 802.16d/e
    • Test and Measurement Instrumentation
    • High Definition Video
    • Medical Imaging
    • Radar Systems

The ADS61B49 (ADS61B29) is a 14-bit (12-bit) A/D converter with a sampling rate up to 250 MSPS. It combines high dynamic performance and low power consumption in a compact 48-QFN package. An integrated analog buffer makes it well-suited for multi-carrier, wide bandwidth communications applications. The buffer maintains constant performance and input impedance across a wide frequency range.

The ADS61B49 (ADS61B29) has fine gain options that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both Double Data Rate (DDR) LVDS and parallel CMOS digital output interfaces are available. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance.

It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The device is specified over the industrial temperature range (-40°C to 85°C).

The ADS61B49 (ADS61B29) is a 14-bit (12-bit) A/D converter with a sampling rate up to 250 MSPS. It combines high dynamic performance and low power consumption in a compact 48-QFN package. An integrated analog buffer makes it well-suited for multi-carrier, wide bandwidth communications applications. The buffer maintains constant performance and input impedance across a wide frequency range.

The ADS61B49 (ADS61B29) has fine gain options that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both Double Data Rate (DDR) LVDS and parallel CMOS digital output interfaces are available. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance.

It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The device is specified over the industrial temperature range (-40°C to 85°C).
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类型 项目标题 下载最新的英语版本 日期
* 数据表 14-/12-Bit, 250-MSPS ADCs with Integrated Analog Input Buffer 数据表 (Rev. B) 2009年 5月 13日
应用手册 Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 2015年 5月 22日
应用手册 Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 2013年 7月 19日
应用手册 Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) 2010年 9月 10日
EVM 用户指南 ADS61x9/55xxEVM User's Guide (Rev B of the EVM board) (Rev. A) 2009年 6月 11日
应用手册 Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 2009年 4月 28日
应用手册 所选封装材料的热学和电学性质 2008年 10月 16日
应用手册 模数规格和性能特性术语表 (Rev. A) 下载最新的英文版本 (Rev.B) 2008年 10月 16日
应用手册 高速数据转换 下载英文版本 2008年 10月 16日
应用手册 CDCE62005 as Clock Solution for High-Speed ADCs 2008年 9月 4日
应用手册 CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 2008年 6月 8日
应用手册 Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 2008年 6月 2日
应用手册 QFN Layout Guidelines 2006年 7月 28日

设计和开发

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支持软件

TIGAR Support Files

SBAC120.ZIP (262219 KB)
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仿真模型

ADS61xx, ADS62Pxx HS IBIS Model (Rev. B)

SLWC088B.ZIP (653 KB) - IBIS Model
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计算工具

JITTER-SNR-CALC — 用于 ADC 的抖动和 SNR 计算器

JITTER-SNR-CALC 可用于根据输入频率和时钟抖动来计算 ADC 的理论信噪比 (SNR) 性能。
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设计工具

TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool) (Rev. B)

SBAC119B.ZIP (3547 KB)
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模拟工具

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VQFN (RGZ) 48 了解详情
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订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

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