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数据转换器
模数转换器 (ADC)
高速 ADC (≥10 MSPS)

ADS6145

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14 位、125MSPS 模数转换器 (ADC)

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ADS6145

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产品详情

Sample rate (max) (Msps) 125 Resolution (Bits) 14 Number of input channels 1 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 500 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 417 Architecture Pipeline SNR (dB) 73.9 ENOB (Bits) 11.7 SFDR (dB) 90 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 125 Resolution (Bits) 14 Number of input channels 1 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 500 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 417 Architecture Pipeline SNR (dB) 73.9 ENOB (Bits) 11.7 SFDR (dB) 90 Operating temperature range (°C) -40 to 85 Input buffer No
VQFN (RHB) 32 25 mm² 5 x 5
  • Maximum Sample Rate: 125 MSPS
  • 14-Bit Resolution with No Missing Codes
  • 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR/SFDR Trade-Off
  • Parallel CMOS and Double Data Rate (DDR) LVDS Output Options
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs, and Clock Amplitude Down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • Internal Reference with Support for External Reference
  • No External Decoupling Required for References
  • Programmable Output Clock Position and Drive Strength to Ease Data Capture
  • 3.3-V Analog and 1.8-V to 3.3-V Digital Supply
  • 32-QFN Package (5 mm × 5 mm)
  • Pin Compatible 12-Bit Family (ADS612X)
  • APPLICATIONS
    • Wireless Communications Infrastructure
    • Software Defined Radio
    • Power Amplifier Linearization
    • 802.16d/e
    • Test and Measurement Instrumentation
    • High Definition Video
    • Medical Imaging
    • Radar Systems
  • Maximum Sample Rate: 125 MSPS
  • 14-Bit Resolution with No Missing Codes
  • 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR/SFDR Trade-Off
  • Parallel CMOS and Double Data Rate (DDR) LVDS Output Options
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs, and Clock Amplitude Down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • Internal Reference with Support for External Reference
  • No External Decoupling Required for References
  • Programmable Output Clock Position and Drive Strength to Ease Data Capture
  • 3.3-V Analog and 1.8-V to 3.3-V Digital Supply
  • 32-QFN Package (5 mm × 5 mm)
  • Pin Compatible 12-Bit Family (ADS612X)
  • APPLICATIONS
    • Wireless Communications Infrastructure
    • Software Defined Radio
    • Power Amplifier Linearization
    • 802.16d/e
    • Test and Measurement Instrumentation
    • High Definition Video
    • Medical Imaging
    • Radar Systems

ADS6145/ADS6144/ADS6143/ADS6142 (ADS614X) are a family of 14-bit A/D converters with sampling frequencies up to 125 MSPS. The high performance and low power consumption of the ADS614X are combined in a compact 32 QFN package. An internal high bandwidth sample and hold and a low jitter clock buffer help to achieve high SNR and high SFDR even at high input frequencies.

The ADS614X feature coarse and fine gain options to improve SFDR performance at lower full-scale analog input ranges.

The digital data outputs are either parallel CMOS or DDR (Double Data Rate) LVDS. Several features exist to ease data capture such as — controls for output clock position and output buffer drive strength, LVDS current, and internal termination programmability.

The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some functions are configured using dedicated parallel pins so the device powers up to the desired state.

The ADS614X include internal references while eliminating traditional reference pins and associated external decoupling. External reference mode is also supported.

The ADS614X are specified over the industrial temperature range (-40°C to 85°C).

ADS6145/ADS6144/ADS6143/ADS6142 (ADS614X) are a family of 14-bit A/D converters with sampling frequencies up to 125 MSPS. The high performance and low power consumption of the ADS614X are combined in a compact 32 QFN package. An internal high bandwidth sample and hold and a low jitter clock buffer help to achieve high SNR and high SFDR even at high input frequencies.

The ADS614X feature coarse and fine gain options to improve SFDR performance at lower full-scale analog input ranges.

The digital data outputs are either parallel CMOS or DDR (Double Data Rate) LVDS. Several features exist to ease data capture such as — controls for output clock position and output buffer drive strength, LVDS current, and internal termination programmability.

The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some functions are configured using dedicated parallel pins so the device powers up to the desired state.

The ADS614X include internal references while eliminating traditional reference pins and associated external decoupling. External reference mode is also supported.

The ADS614X are specified over the industrial temperature range (-40°C to 85°C).

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS 数据表 (Rev. B) 2007年 12月 4日
应用手册 Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 2015年 5月 22日
应用手册 Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 2013年 7月 19日
应用手册 Band-Pass Filter Design Techniques for High-Speed ADCs 2012年 2月 27日
应用手册 Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) 2010年 9月 10日
应用手册 Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 2009年 4月 28日
应用手册 所选封装材料的热学和电学性质 2008年 10月 16日
应用手册 模数规格和性能特性术语表 (Rev. A) 最新英语版本 (Rev.B) 2008年 10月 16日
应用手册 高速数据转换 英语版 2008年 10月 16日
应用手册 CDCE62005 as Clock Solution for High-Speed ADCs 2008年 9月 4日
应用手册 CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 2008年 6月 8日
应用手册 Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 2008年 6月 2日
应用手册 QFN Layout Guidelines 2006年 7月 28日

设计与开发

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评估模块 (EVM) 用 GUI

DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

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支持软件

HSADC-SPI-UTILITY — ADS5400 EVM GUI

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仿真模型

ADS61xx IBIS Model

SLAC211.ZIP (915 KB) - IBIS Model
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计算工具

ADC-HARMONIC-CALC — ADC Frequency Calculator Download

    The ADC Harmonic Calculation tool is an excel based calculator for determining the location in frequency space of high order harmonics following Nyquist aliasing in an analog to digital converter.

    Given an ADC sample rate and the span of a signal of interest the calcultor will determine if the 2nd (...)

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计算工具

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

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计算工具

JITTER-SNR-CALC — Jitter and SNR calculator

JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.

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设计工具

SBAC119 — TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)

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模拟工具

PSPICE-FOR-TI — PSpice® for TI 设计和仿真工具

PSpice® for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence® 的模拟分析引擎。PSpice for TI 可免费使用，包括业内超大的模型库之一，涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助 PSpice for TI 的设计和仿真环境及其内置的模型库，您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案，然后再进行布局和制造，可缩短产品上市时间并降低开发成本。 

在 PSpice for TI 设计和仿真工具中，您可以搜索 TI (...)
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VQFN (RHB) 32 Ultra Librarian
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包含信息：
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  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
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  • 封装厂地点

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