产品详细信息

Sample rate (Max) (MSPS) 80 Resolution (Bits) 12 Number of input channels 2 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 450 Features High Performance Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 587 Architecture Pipeline SNR (dB) 71.6 ENOB (Bits) 11.6 SFDR (dB) 93 Operating temperature range (C) -40 to 85 Input buffer No
Sample rate (Max) (MSPS) 80 Resolution (Bits) 12 Number of input channels 2 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 450 Features High Performance Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 587 Architecture Pipeline SNR (dB) 71.6 ENOB (Bits) 11.6 SFDR (dB) 93 Operating temperature range (C) -40 to 85 Input buffer No
VQFN (RGC) 64 81 mm² 9 x 9
  • Maximum Sample Rate: 125 MSPS
  • 12-Bit Resolution with No Missing Codes
  • 95 dB Crosstalk
  • Parallel CMOS and DDR LVDS Output Options
  • 3.5 dB Coarse Gain and Programmable Fine Gain
    up to 6 dB for SNR/SFDR Trade-Off
  • Digital Processing Block with:
    • Offset Correction
    • Fine Gain Correction, in Steps of 0.05 dB
    • Decimation by 2/4/8
    • Built-in and Custom Programmable
      24-Tap Low-/High-/Band-Pass Filters
  • Supports Sine, LVPECL, LVDS, and LVCMOS Clocks and
    Amplitude Down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • Internal Reference; Supports External Reference also
  • 64-QFN Package (9mm × 9mm)
  • Pin Compatible 14-Bit Family (ADS62P4X)
  • Maximum Sample Rate: 125 MSPS
  • 12-Bit Resolution with No Missing Codes
  • 95 dB Crosstalk
  • Parallel CMOS and DDR LVDS Output Options
  • 3.5 dB Coarse Gain and Programmable Fine Gain
    up to 6 dB for SNR/SFDR Trade-Off
  • Digital Processing Block with:
    • Offset Correction
    • Fine Gain Correction, in Steps of 0.05 dB
    • Decimation by 2/4/8
    • Built-in and Custom Programmable
      24-Tap Low-/High-/Band-Pass Filters
  • Supports Sine, LVPECL, LVDS, and LVCMOS Clocks and
    Amplitude Down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • Internal Reference; Supports External Reference also
  • 64-QFN Package (9mm × 9mm)
  • Pin Compatible 14-Bit Family (ADS62P4X)

ADS62P2X is a dual channel 12-bit A/D converter family with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.

ADS62P2X includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.

Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P2X includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).

ADS62P2X is a dual channel 12-bit A/D converter family with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.

ADS62P2X includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.

Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P2X includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).

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技术文档

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类型 项目标题 下载最新的英语版本 日期
* 数据表 Dual Channel, 12Bit, 125/105/80/65 MSPS ADC with DDR LVDS/CMOS Outputs 数据表 (Rev. C) 11 May 2011
应用手册 Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
应用手册 Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013
用户指南 TSW4200 Demonstration Kit User's Guide (Rev. C) 31 Oct 2012
用户指南 Interfacing Altera FPGA with ADS4249 and DAC3482 10 Jul 2012
应用手册 Anti-aliasing band-pass filter for ADC 27 Feb 2012
应用手册 Driving High Speed A/D Converters (Rev. A) 10 Sep 2010
应用手册 Smart Selection of ADC/DAC enables better design of Software Defined Radio (SDR) 28 Apr 2009
用户指南 ADS62PxxEVM Quick Start Guide (Rev C Board) (Rev. A) 02 Apr 2009
EVM 用户指南 ADS62PXX EVM User's Guide (Rev. A) 23 Feb 2009
应用手册 所选封装材料的热学和电学性质 16 Oct 2008
应用手册 模数规格和性能特性术语表 (Rev. A) 下载最新的英文版本 (Rev.B) 16 Oct 2008
应用手册 高速数据转换 下载英文版本 16 Oct 2008
应用手册 CDCE62005 Application Report 04 Sep 2008
应用手册 CDCE72010 as clocking solution for High Speed Analog-to-Digital Converters 08 Jun 2008
应用手册 Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 02 Jun 2008
EVM 用户指南 ADS62P15EVM User's Guide 21 May 2008
应用手册 QFN Layout Guidelines 28 Jul 2006

设计和开发

如需其他信息或资源,请查看下方列表,点击标题即可进入详情页面。

评估板

ADS62P23EVM — ADS62P23 评估模块

ADS62P23 EVM 是能让设计者评估德州仪器 (TI) ADS62P23 器件(双通道 12 位 80MSPS 模数转换器)的电路板。ADC 具有用户可选的并行 CMOS 或 DDR LVDS 输出。用户可以使用 TSW1100(CMOS 模式)或 TSW1200EVM(DDR LVDS 模式)从转换器采集数据。EVM 提供了可在各种时钟、输入和电源条件下测试 ADS62P23 的灵活环境。

评估板还能让设计者在 ADC 中使用变压器耦合输入或基于德州仪器 (TI) THS4509 的放大器输入。由于 ADC EVM 提供 THS4509,用户可以轻松评估所有与封装兼容的 ADC (...)

用户指南: PDF
软件编程工具

HSADC-SPI-UTILITY — 高速 ADC SPI 编程工具

支持软件

DATACONVERTERPRO-SW — High Speed Data Converter Pro 软件

此高速数据转换器专业 GUI 是一款 PC 程序(兼容 Windows® XP/7/10),旨在帮助评估大多数 TI 高速数据转换器和模拟前端 (AFE) 平台。DATACONVERTERPRO-SW 支持整个 TSW14xxx 系列的数据采集和模式生成卡,为分析时域和频域中的数据转换器提供了快速强大的解决方案以及单音调、多音调和调制信号支持。此 GUI 还兼容用于快速合成单音调、多音调和调制信号的 TI 模式生成 GUI。

用户可以为 DATACONVERTERPRO-SW 提供定制模式,以加载到 TI 数模转换器 (DAC)。支持从模数转换器 (ADC) 采集内导出 CSV (...)

用户指南: PDF | HTML
仿真模型

ADS62Pxx Family TINA-TI Transient Spice Model

SBAM007.TSM (14 KB) - TINA-TI Spice Model
仿真模型

ADS62Pxx Family TINA-TI Transient Reference Design

SBAM008.ZIP (6 KB) - TINA-TI Reference Design
仿真模型

ADS62Pxx IBIS Model (Rev. A)

SLAC176A.ZIP (921 KB) - IBIS Model
模拟工具

PSPICE-FOR-TI — 适用于 TI 设计和模拟工具的 PSpice®

PSpice® for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence® 的模拟分析引擎。PSpice for TI 可免费使用,包括业内超大的模型库之一,涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助 PSpice for TI 的设计和仿真环境及其内置的模型库,您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案,然后再进行布局和制造,可缩短产品上市时间并降低开发成本。

在 PSpice for TI 设计和仿真工具中,您可以搜索 TI (...)
计算工具

ADC-HARMONIC-CALC — 模数转换器 (ADC) 谐波计算器

    ADC 谐波计算工具是基于 excel 的计算器,用于确定当模数转换器中出现奈奎斯特混叠后高次谐波的频率空间的位置。

    如果给定 ADC 采样速率和有用信号的范围,该计算器可以确定第 2 至第 9 谐波是否会返送到有用信号的频带中。图表以图形方式显示了在出现奈奎斯特混叠后基本信号以及第 2 至第 9 谐波的位置。

封装 引脚数 下载
VQFN (RGC) 64 了解详情

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

支持与培训

视频