| 31-9 |
RESERVED |
R |
0x0 |
|
| 8 |
RXFFMIS |
R |
0x0 |
Receive FIFO Full Interrupt Mask. This bit is cleared by writing a 1 to the RXFFIC bit in the I2CSICR register.
0x0 = No interrupt.
0x1 = An unmasked Receive FIFO Full interrupt was signaled and is pending.
|
| 7 |
TXFEMIS |
R |
0x0 |
Transmit FIFO Empty Interrupt Mask. This bit is cleared by writing a 1 to the TXFEIC bit in the I2CSICR register.
0x0 = No interrupt.
0x1 = An unmasked Transmit FIFO Empty interrupt was signaled and is pending.
|
| 6 |
RXMIS |
R |
0x0 |
Receive FIFO Request Interrupt Mask. This bit is cleared by writing a 1 to the RXIC bit in the I2CSICR register.
0x0 = No interrupt.
0x1 = An unmasked Receive FIFO Request interrupt was signaled and is pending.
|
| 5 |
TXMIS |
R |
0x0 |
Transmit FIFO Request Interrupt Mask. This bit is cleared by writing a 1 to the TXIC bit in the I2CSICR register.
0x0 = No interrupt.
0x1 = An unmasked Transmit FIFO Request interrupt was signaled and is pending.
|
| 4 |
DMATXMIS |
R |
0x0 |
Transmit DMA Masked Interrupt Status. This bit is cleared by writing a 1 to the DMATXIC bit in the I2CSICR register.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked transmit DMA complete interrupt was signaled is pending.
|
| 3 |
DMARXMIS |
R |
0x0 |
Receive DMA Masked Interrupt Status. This bit is cleared by writing a 1 to the DMARXIC bit in the I2CSICR register.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked receive DMA complete interrupt was signaled is pending.
|
| 2 |
STOPMIS |
R |
0x0 |
Stop Condition Masked Interrupt Status. This bit is cleared by writing a 1 to the STOPIC bit in the I2CSICR register.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked STOP condition interrupt was signaled is pending.
|
| 1 |
STARTMIS |
R |
0x0 |
Start Condition Masked Interrupt Status. This bit is cleared by writing a 1 to the STARTIC bit in the I2CSICR register.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked START condition interrupt was signaled is pending.
|
| 0 |
DATAMIS |
R |
0x0 |
Data Masked Interrupt Status. This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR register.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked slave data interrupt was signaled is pending.
|