SLAU723A October 2017 ā October 2018 MSP432E401Y , MSP432E411Y
The CRC Control (CRCCTRL) register is used to configure control of the CRC.
CRCCTRL is shown in Figure 13-1 and described in Table 13-5.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | INIT | SIZE | RESERVED | RESINV | OBR | ||
| R-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BR | RESERVED | ENDIAN | TYPE | ||||
| R/W-0h | R-0h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-15 | RESERVED | R | 0h |
|
| 14-13 | INIT | R/W | 0h | CRC Initialization.
Determines initialization value of CRC. This field is self-clearing. With the first write to the CRC Data Input (CRCDIN) register, this value clears to zero and remains zero for the rest of the operation unless written again. 0h = Use the CRCSEED register context as the starting value 1h = reserved 2h = Initialize to all 0s 3h = Initialize to all 1s |
| 12 | SIZE | R/W | 0h |
Input Data Size. 0h = 32-bit (word) 1h = 8-bit (byte) |
| 11-10 | RESERVED | R | 0h |
|
| 9 | RESINV | R/W | 0h |
Result Inverse Enable. 0h = No effect 1h = Invert the result bits before storing in the CRCRSLTPP register. |
| 8 | OBR | R/W | 0h |
Output Reverse Enable See Table 13-2 for more information regarding bit reversal. 0h = No change to result. 1h = Bit reverse the output result byte before storing to CRCRSLTPP register. The reversal is applied to all bytes in a word. |
| 7 | BR | R/W | 0h | Bit reverse enable.
See Table 13-2 for more information regarding bit reversal. 0h = No change to result. 1h = Bit reverse the input byte for all bytes in a word. |
| 6 | RESERVED | R | 0h |
|
| 5-4 | ENDIAN | R/W | 0h | Endian Control.
This field is used to program the endian configuration. The encodings below are with respect to an input word = (B3, B2, B1, B0). See Table 13-1 for more information regarding endian configuration and control. 0h = Configuration unchanged. (B3, B2, B1, B0) 1h = Bytes are swapped in half-words but half-words are not swapped (B2, B3, B0, B1) 2h = Half-words are swapped but bytes are not swapped in half-word. (B1, B0, B3, B2) 3h = Bytes are swapped in half-words and half-words are swapped. (B0, B1, B2, B3) |
| 3-0 | TYPE | R/W | 0h | Operation Type.
The TYPE value in the CRCCTRL register should be exclusive. 0h = Polynomial 0x8005 1h = Polynomial 0x1021 2h = Polynomial 0x4C11DB7 3h = Polynomial 0x1EDC6F41 8h = TCP checksum |