SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The USB controller has On-The-Go (OTG) capabilities.
OTG B / Device indicates that the register is used in OTG B or Device mode. Some registers are used for both Host and Device mode and may have different bit definitions depending on the mode.
OTG A / Host indicates that the register is used in OTG A or Host mode. Some registers are used for both Host and Device mode and may have different bit definitions depending on the mode. The USB controller is in OTG B or Device mode upon reset, so the reset values shown for these registers apply to the Device mode definition.
OTG indicates that the register is used for OTG-specific functions such as ID detection and negotiation. When OTG negotiation is complete, then the USB controller registers are used according to their Host or Device mode meanings depending on whether the OTG negotiations made the USB controller OTG A (Host) or OTG B (Device).
Table 27-5 lists the memory-mapped registers for the USB. All register offset addresses not listed in Table 27-5 should be considered as reserved locations and the register contents should not be modified.
All offsets are relative to the USB base address of 0x40050000. The USB controller clock must be enabled before the registers can be programmed. There must be a delay of 3 system clock cycles after the USB module clock is enabled before any USB module registers are accessed.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0x0 | USBFADDR | USB Device Functional Address | Section 27.5.1 |
| 0x1 | USBPOWER | USB Power | Section 27.5.2 |
| 0x2 | USBTXIS | USB Transmit Interrupt Status | Section 27.5.3 |
| 0x4 | USBRXIS | USB Receive Interrupt Status | Section 27.5.4 |
| 0x6 | USBTXIE | USB Transmit Interrupt Enable | Section 27.5.5 |
| 0x8 | USBRXIE | USB Receive Interrupt Enable | Section 27.5.6 |
| 0xA | USBIS | USB General Interrupt Status | Section 27.5.7 |
| 0xB | USBIE | USB Interrupt Enable | Section 27.5.8 |
| 0xC | USBFRAME | USB Frame Value | Section 27.5.9 |
| 0xE | USBEPIDX | USB Endpoint Index | Section 27.5.10 |
| 0xF | USBTEST | USB Test Mode | Section 27.5.11 |
| 0x20 | USBFIFO0 | USB FIFO Endpoint 0 | Section 27.5.12 |
| 0x24 | USBFIFO1 | USB FIFO Endpoint 1 | Section 27.5.12 |
| 0x28 | USBFIFO2 | USB FIFO Endpoint 2 | Section 27.5.12 |
| 0x2C | USBFIFO3 | USB FIFO Endpoint 3 | Section 27.5.12 |
| 0x30 | USBFIFO4 | USB FIFO Endpoint 4 | Section 27.5.12 |
| 0x34 | USBFIFO5 | USB FIFO Endpoint 5 | Section 27.5.12 |
| 0x38 | USBFIFO6 | USB FIFO Endpoint 6 | Section 27.5.12 |
| 0x3C | USBFIFO7 | USB FIFO Endpoint 7 | Section 27.5.12 |
| 0x60 | USBDEVCTL | USB Device Control | Section 27.5.13 |
| 0x61 | USBCCONF | USB Common Configuration | Section 27.5.14 |
| 0x62 | USBTXFIFOSZ | USB Transmit Dynamic FIFO Sizing | Section 27.5.15 |
| 0x63 | USBRXFIFOSZ | USB Receive Dynamic FIFO Sizing | Section 27.5.15 |
| 0x64 | USBTXFIFOADD | USB Transmit FIFO Start Address | Section 27.5.16 |
| 0x66 | USBRXFIFOADD | USB Receive FIFO Start Address | Section 27.5.16 |
| 0x70 | ULPIVBUSCTL | USB ULPI VBUS Control | Section 27.5.17 |
| 0x74 | ULPIREGDATA | USB ULPI Register Data | Section 27.5.18 |
| 0x75 | ULPIREGADDR | USB ULPI Register Address | Section 27.5.19 |
| 0x76 | ULPIREGCTL | USB ULPI Register Control | Section 27.5.20 |
| 0x78 | USBEPINFO | USB Endpoint Information | Section 27.5.21 |
| 0x79 | USBRAMINFO | USB RAM Information | Section 27.5.22 |
| 0x7A | USBCONTIM | USB Connect Timing | Section 27.5.23 |
| 0x7B | USBVPLEN | USB OTG VBUS Pulse Timing | Section 27.5.24 |
| 0x7C | USBHSEOF | USB High-Speed Last Transaction to End of Frame Timing | Section 27.5.25 |
| 0x7D | USBFSEOF | USB Full-Speed Last Transaction to End of Frame Timing | Section 27.5.26 |
| 0x7E | USBLSEOF | USB Low-Speed Last Transaction to End of Frame Timing | Section 27.5.27 |
| 0x80 | USBTXFUNCADDR0 | USB Transmit Functional Address Endpoint 0 | Section 27.5.28 |
| 0x82 | USBTXHUBADDR0 | USB Transmit Hub Address Endpoint 0 | Section 27.5.29 |
| 0x83 | USBTXHUBPORT0 | USB Transmit Hub Port Endpoint 0 | Section 27.5.30 |
| 0x88 | USBTXFUNCADDR1 | USB Transmit Functional Address Endpoint 1 | Section 27.5.28 |
| 0x8A | USBTXHUBADDR1 | USB Transmit Hub Address Endpoint 1 | Section 27.5.29 |
| 0x8B | USBTXHUBPORT1 | USB Transmit Hub Port Endpoint 1 | Section 27.5.30 |
| 0x8C | USBRXFUNCADDR1 | USB Receive Functional Address Endpoint 1 | Section 27.5.31 |
| 0x8E | USBRXHUBADDR1 | USB Receive Hub Address Endpoint 1 | Section 27.5.32 |
| 0x8F | USBRXHUBPORT1 | USB Receive Hub Port Endpoint 1 | Section 27.5.33 |
| 0x90 | USBTXFUNCADDR2 | USB Transmit Functional Address Endpoint 2 | Section 27.5.28 |
| 0x92 | USBTXHUBADDR2 | USB Transmit Hub Address Endpoint 2 | Section 27.5.29 |
| 0x93 | USBTXHUBPORT2 | USB Transmit Hub Port Endpoint 2 | Section 27.5.30 |
| 0x94 | USBRXFUNCADDR2 | USB Receive Functional Address Endpoint 2 | Section 27.5.31 |
| 0x96 | USBRXHUBADDR2 | USB Receive Hub Address Endpoint 2 | Section 27.5.32 |
| 0x97 | USBRXHUBPORT2 | USB Receive Hub Port Endpoint 2 | Section 27.5.33 |
| 0x98 | USBTXFUNCADDR3 | USB Transmit Functional Address Endpoint 3 | Section 27.5.28 |
| 0x9A | USBTXHUBADDR3 | USB Transmit Hub Address Endpoint 3 | Section 27.5.29 |
| 0x9B | USBTXHUBPORT3 | USB Transmit Hub Port Endpoint 3 | Section 27.5.30 |
| 0x9C | USBRXFUNCADDR3 | USB Receive Functional Address Endpoint 3 | Section 27.5.31 |
| 0x9E | USBRXHUBADDR3 | USB Receive Hub Address Endpoint 3 | Section 27.5.32 |
| 0x9F | USBRXHUBPORT3 | USB Receive Hub Port Endpoint 3 | Section 27.5.33 |
| 0xA0 | USBTXFUNCADDR4 | USB Transmit Functional Address Endpoint 4 | Section 27.5.28 |
| 0xA2 | USBTXHUBADDR4 | USB Transmit Hub Address Endpoint 4 | Section 27.5.29 |
| 0xA3 | USBTXHUBPORT4 | USB Transmit Hub Port Endpoint 4 | Section 27.5.30 |
| 0xA4 | USBRXFUNCADDR4 | USB Receive Functional Address Endpoint 4 | Section 27.5.31 |
| 0xA6 | USBRXHUBADDR4 | USB Receive Hub Address Endpoint 4 | Section 27.5.32 |
| 0xA7 | USBRXHUBPORT4 | USB Receive Hub Port Endpoint 4 | Section 27.5.33 |
| 0xA8 | USBTXFUNCADDR5 | USB Transmit Functional Address Endpoint 5 | Section 27.5.28 |
| 0xAA | USBTXHUBADDR5 | USB Transmit Hub Address Endpoint 5 | Section 27.5.29 |
| 0xAB | USBTXHUBPORT5 | USB Transmit Hub Port Endpoint 5 | Section 27.5.30 |
| 0xAC | USBRXFUNCADDR5 | USB Receive Functional Address Endpoint 5 | Section 27.5.31 |
| 0xAE | USBRXHUBADDR5 | USB Receive Hub Address Endpoint 5 | Section 27.5.32 |
| 0xAF | USBRXHUBPORT5 | USB Receive Hub Port Endpoint 5 | Section 27.5.33 |
| 0xB0 | USBTXFUNCADDR6 | USB Transmit Functional Address Endpoint 6 | Section 27.5.28 |
| 0xB2 | USBTXHUBADDR6 | USB Transmit Hub Address Endpoint 6 | Section 27.5.29 |
| 0xB3 | USBTXHUBPORT6 | USB Transmit Hub Port Endpoint 6 | Section 27.5.30 |
| 0xB4 | USBRXFUNCADDR6 | USB Receive Functional Address Endpoint 6 | Section 27.5.31 |
| 0xB6 | USBRXHUBADDR6 | USB Receive Hub Address Endpoint 6 | Section 27.5.32 |
| 0xB7 | USBRXHUBPORT6 | USB Receive Hub Port Endpoint 6 | Section 27.5.33 |
| 0xB8 | USBTXFUNCADDR7 | USB Transmit Functional Address Endpoint 7 | Section 27.5.28 |
| 0xBA | USBTXHUBADDR7 | USB Transmit Hub Address Endpoint 7 | Section 27.5.29 |
| 0xBB | USBTXHUBPORT7 | USB Transmit Hub Port Endpoint 7 | Section 27.5.30 |
| 0xBC | USBRXFUNCADDR7 | USB Receive Functional Address Endpoint 7 | Section 27.5.31 |
| 0xBE | USBRXHUBADDR7 | USB Receive Hub Address Endpoint 7 | Section 27.5.32 |
| 0xBF | USBRXHUBPORT7 | USB Receive Hub Port Endpoint 7 | Section 27.5.33 |
| 0x102 | USBCSRL0 | USB Control and Status Endpoint 0 Low | Section 27.5.34 |
| 0x103 | USBCSRH0 | USB Control and Status Endpoint 0 High | Section 27.5.35 |
| 0x108 | USBCOUNT0 | USB Receive Byte Count Endpoint 0 | Section 27.5.36 |
| 0x10A | USBTYPE0 | USB Type Endpoint 0 | Section 27.5.37 |
| 0x10B | USBNAKLMT | USB NAK Limit | Section 27.5.38 |
| 0x110 | USBTXMAXP1 | USB Maximum Transmit Data Endpoint 1 | Section 27.5.39 |
| 0x112 | USBTXCSRL1 | USB Transmit Control and Status Endpoint 1 Low | Section 27.5.40 |
| 0x113 | USBTXCSRH1 | USB Transmit Control and Status Endpoint 1 High | Section 27.5.41 |
| 0x114 | USBRXMAXP1 | USB Maximum Receive Data Endpoint 1 | Section 27.5.42 |
| 0x116 | USBRXCSRL1 | USB Receive Control and Status Endpoint 1 Low | Section 27.5.43 |
| 0x117 | USBRXCSRH1 | USB Receive Control and Status Endpoint 1 High | Section 27.5.44 |
| 0x118 | USBRXCOUNT1 | USB Receive Byte Count Endpoint 1 | Section 27.5.45 |
| 0x11A | USBTXTYPE1 | USB Host Transmit Configure Type Endpoint 1 | Section 27.5.46 |
| 0x11B | USBTXINTERVAL1 | USB Host Transmit Interval Endpoint 1 | Section 27.5.47 |
| 0x11C | USBRXTYPE1 | USB Host Configure Receive Type Endpoint 1 | Section 27.5.48 |
| 0x11D | USBRXINTERVAL1 | USB Host Receive Polling Interval Endpoint 1 | Section 27.5.49 |
| 0x120 | USBTXMAXP2 | USB Maximum Transmit Data Endpoint 2 | Section 27.5.39 |
| 0x122 | USBTXCSRL2 | USB Transmit Control and Status Endpoint 2 Low | Section 27.5.40 |
| 0x123 | USBTXCSRH2 | USB Transmit Control and Status Endpoint 2 High | Section 27.5.41 |
| 0x124 | USBRXMAXP2 | USB Maximum Receive Data Endpoint 2 | Section 27.5.42 |
| 0x126 | USBRXCSRL2 | USB Receive Control and Status Endpoint 2 Low | Section 27.5.43 |
| 0x127 | USBRXCSRH2 | USB Receive Control and Status Endpoint 2 High | Section 27.5.44 |
| 0x128 | USBRXCOUNT2 | USB Receive Byte Count Endpoint 2 | Section 27.5.45 |
| 0x12A | USBTXTYPE2 | USB Host Transmit Configure Type Endpoint 2 | Section 27.5.46 |
| 0x12B | USBTXINTERVAL2 | USB Host Transmit Interval Endpoint 2 | Section 27.5.47 |
| 0x12C | USBRXTYPE2 | USB Host Configure Receive Type Endpoint 2 | Section 27.5.48 |
| 0x12D | USBRXINTERVAL2 | USB Host Receive Polling Interval Endpoint 2 | Section 27.5.49 |
| 0x130 | USBTXMAXP3 | USB Maximum Transmit Data Endpoint 3 | Section 27.5.39 |
| 0x132 | USBTXCSRL3 | USB Transmit Control and Status Endpoint 3 Low | Section 27.5.40 |
| 0x133 | USBTXCSRH3 | USB Transmit Control and Status Endpoint 3 High | Section 27.5.41 |
| 0x134 | USBRXMAXP3 | USB Maximum Receive Data Endpoint 3 | Section 27.5.42 |
| 0x136 | USBRXCSRL3 | USB Receive Control and Status Endpoint 3 Low | Section 27.5.43 |
| 0x137 | USBRXCSRH3 | USB Receive Control and Status Endpoint 3 High | Section 27.5.44 |
| 0x138 | USBRXCOUNT3 | USB Receive Byte Count Endpoint 3 | Section 27.5.45 |
| 0x13A | USBTXTYPE3 | USB Host Transmit Configure Type Endpoint 3 | Section 27.5.46 |
| 0x13B | USBTXINTERVAL3 | USB Host Transmit Interval Endpoint 3 | Section 27.5.47 |
| 0x13C | USBRXTYPE3 | USB Host Configure Receive Type Endpoint 3 | Section 27.5.48 |
| 0x13D | USBRXINTERVAL3 | USB Host Receive Polling Interval Endpoint 3 | Section 27.5.49 |
| 0x140 | USBTXMAXP4 | USB Maximum Transmit Data Endpoint 4 | Section 27.5.39 |
| 0x142 | USBTXCSRL4 | USB Transmit Control and Status Endpoint 4 Low | Section 27.5.40 |
| 0x143 | USBTXCSRH4 | USB Transmit Control and Status Endpoint 4 High | Section 27.5.41 |
| 0x144 | USBRXMAXP4 | USB Maximum Receive Data Endpoint 4 | Section 27.5.42 |
| 0x146 | USBRXCSRL4 | USB Receive Control and Status Endpoint 4 Low | Section 27.5.43 |
| 0x147 | USBRXCSRH4 | USB Receive Control and Status Endpoint 4 High | Section 27.5.44 |
| 0x148 | USBRXCOUNT4 | USB Receive Byte Count Endpoint 4 | Section 27.5.45 |
| 0x14A | USBTXTYPE4 | USB Host Transmit Configure Type Endpoint 4 | Section 27.5.46 |
| 0x14B | USBTXINTERVAL4 | USB Host Transmit Interval Endpoint 4 | Section 27.5.47 |
| 0x14C | USBRXTYPE4 | USB Host Configure Receive Type Endpoint 4 | Section 27.5.48 |
| 0x14D | USBRXINTERVAL4 | USB Host Receive Polling Interval Endpoint 4 | Section 27.5.49 |
| 0x150 | USBTXMAXP5 | USB Maximum Transmit Data Endpoint 5 | Section 27.5.39 |
| 0x152 | USBTXCSRL5 | USB Transmit Control and Status Endpoint 5 Low | Section 27.5.40 |
| 0x153 | USBTXCSRH5 | USB Transmit Control and Status Endpoint 5 High | Section 27.5.41 |
| 0x154 | USBRXMAXP5 | USB Maximum Receive Data Endpoint 5 | Section 27.5.42 |
| 0x156 | USBRXCSRL5 | USB Receive Control and Status Endpoint 5 Low | Section 27.5.43 |
| 0x157 | USBRXCSRH5 | USB Receive Control and Status Endpoint 5 High | Section 27.5.44 |
| 0x158 | USBRXCOUNT5 | USB Receive Byte Count Endpoint 5 | Section 27.5.45 |
| 0x15A | USBTXTYPE5 | USB Host Transmit Configure Type Endpoint 5 | Section 27.5.46 |
| 0x15B | USBTXINTERVAL5 | USB Host Transmit Interval Endpoint 5 | Section 27.5.47 |
| 0x15C | USBRXTYPE5 | USB Host Configure Receive Type Endpoint 5 | Section 27.5.48 |
| 0x15D | USBRXINTERVAL5 | USB Host Receive Polling Interval Endpoint 5 | Section 27.5.49 |
| 0x160 | USBTXMAXP6 | USB Maximum Transmit Data Endpoint 6 | Section 27.5.39 |
| 0x162 | USBTXCSRL6 | USB Transmit Control and Status Endpoint 6 Low | Section 27.5.40 |
| 0x163 | USBTXCSRH6 | USB Transmit Control and Status Endpoint 6 High | Section 27.5.41 |
| 0x164 | USBRXMAXP6 | USB Maximum Receive Data Endpoint 6 | Section 27.5.42 |
| 0x166 | USBRXCSRL6 | USB Receive Control and Status Endpoint 6 Low | Section 27.5.43 |
| 0x167 | USBRXCSRH6 | USB Receive Control and Status Endpoint 6 High | Section 27.5.44 |
| 0x168 | USBRXCOUNT6 | USB Receive Byte Count Endpoint 6 | Section 27.5.45 |
| 0x16A | USBTXTYPE6 | USB Host Transmit Configure Type Endpoint 6 | Section 27.5.46 |
| 0x16B | USBTXINTERVAL6 | USB Host Transmit Interval Endpoint 6 | Section 27.5.47 |
| 0x16C | USBRXTYPE6 | USB Host Configure Receive Type Endpoint 6 | Section 27.5.48 |
| 0x16D | USBRXINTERVAL6 | USB Host Receive Polling Interval Endpoint 6 | Section 27.5.49 |
| 0x170 | USBTXMAXP7 | USB Maximum Transmit Data Endpoint 7 | Section 27.5.39 |
| 0x172 | USBTXCSRL7 | USB Transmit Control and Status Endpoint 7 Low | Section 27.5.40 |
| 0x173 | USBTXCSRH7 | USB Transmit Control and Status Endpoint 7 High | Section 27.5.41 |
| 0x174 | USBRXMAXP7 | USB Maximum Receive Data Endpoint 7 | Section 27.5.42 |
| 0x176 | USBRXCSRL7 | USB Receive Control and Status Endpoint 7 Low | Section 27.5.43 |
| 0x177 | USBRXCSRH7 | USB Receive Control and Status Endpoint 7 High | Section 27.5.44 |
| 0x178 | USBRXCOUNT7 | USB Receive Byte Count Endpoint 7 | Section 27.5.45 |
| 0x17A | USBTXTYPE7 | USB Host Transmit Configure Type Endpoint 7 | Section 27.5.46 |
| 0x17B | USBTXINTERVAL7 | USB Host Transmit Interval Endpoint 7 | Section 27.5.47 |
| 0x17C | USBRXTYPE7 | USB Host Configure Receive Type Endpoint 7 | Section 27.5.48 |
| 0x17D | USBRXINTERVAL7 | USB Host Receive Polling Interval Endpoint 7 | Section 27.5.49 |
| 0x200 | USBDMAINTR | USB DMA Interrupt | Section 27.5.50 |
| 0x204 | USBDMACTL0 | USB DMA Control 0 | Section 27.5.51 |
| 0x208 | USBDMAADDR0 | USB DMA Address 0 | Section 27.5.52 |
| 0x20C | USBDMACOUNT0 | USB DMA Count 0 | Section 27.5.53 |
| 0x214 | USBDMACTL1 | USB DMA Control 1 | Section 27.5.51 |
| 0x218 | USBDMAADDR1 | USB DMA Address 1 | Section 27.5.52 |
| 0x21C | USBDMACOUNT1 | USB DMA Count 1 | Section 27.5.53 |
| 0x224 | USBDMACTL2 | USB DMA Control 2 | Section 27.5.51 |
| 0x228 | USBDMAADDR2 | USB DMA Address 2 | Section 27.5.52 |
| 0x22C | USBDMACOUNT2 | USB DMA Count 2 | Section 27.5.53 |
| 0x234 | USBDMACTL3 | USB DMA Control 3 | Section 27.5.51 |
| 0x238 | USBDMAADDR3 | USB DMA Address 3 | Section 27.5.52 |
| 0x23C | USBDMACOUNT3 | USB DMA Count 3 | Section 27.5.53 |
| 0x244 | USBDMACTL4 | USB DMA Control 4 | Section 27.5.51 |
| 0x248 | USBDMAADDR4 | USB DMA Address 4 | Section 27.5.52 |
| 0x24C | USBDMACOUNT4 | USB DMA Count 4 | Section 27.5.53 |
| 0x254 | USBDMACTL5 | USB DMA Control 5 | Section 27.5.51 |
| 0x258 | USBDMAADDR5 | USB DMA Address 5 | Section 27.5.52 |
| 0x25C | USBDMACOUNT5 | USB DMA Count 5 | Section 27.5.53 |
| 0x264 | USBDMACTL6 | USB DMA Control 6 | Section 27.5.51 |
| 0x268 | USBDMAADDR6 | USB DMA Address 6 | Section 27.5.52 |
| 0x26C | USBDMACOUNT6 | USB DMA Count 6 | Section 27.5.53 |
| 0x274 | USBDMACTL7 | USB DMA Control 7 | Section 27.5.51 |
| 0x278 | USBDMAADDR7 | USB DMA Address 7 | Section 27.5.52 |
| 0x27C | USBDMACOUNT7 | USB DMA Count 7 | Section 27.5.53 |
| 0x304 | USBRQPKTCOUNT1 | USB Request Packet Count in Block Transfer Endpoint 1 | Section 27.5.54 |
| 0x308 | USBRQPKTCOUNT2 | USB Request Packet Count in Block Transfer Endpoint 2 | Section 27.5.54 |
| 0x30C | USBRQPKTCOUNT3 | USB Request Packet Count in Block Transfer Endpoint 3 | Section 27.5.54 |
| 0x310 | USBRQPKTCOUNT4 | USB Request Packet Count in Block Transfer Endpoint 4 | Section 27.5.54 |
| 0x314 | USBRQPKTCOUNT5 | USB Request Packet Count in Block Transfer Endpoint 5 | Section 27.5.54 |
| 0x318 | USBRQPKTCOUNT6 | USB Request Packet Count in Block Transfer Endpoint 6 | Section 27.5.54 |
| 0x31C | USBRQPKTCOUNT7 | USB Request Packet Count in Block Transfer Endpoint 7 | Section 27.5.54 |
| 0x340 | USBRXDPKTBUFDIS | USB Receive Double Packet Buffer Disable | Section 27.5.55 |
| 0x342 | USBTXDPKTBUFDIS | USB Transmit Double Packet Buffer Disable | Section 27.5.56 |
| 0x344 | USBCTO | USB Chirp Time-out | Section 27.5.57 |
| 0x346 | USBHHSRTN | USB High Speed to UTM Operating Delay | Section 27.5.58 |
| 0x348 | USBHSBT | USB High Speed Time-out Adder | Section 27.5.59 |
| 0x360 | USBLPMATTR | USB LPM Attributes | Section 27.5.60 |
| 0x362 | USBLPMCNTRL | USB LPM Control | Section 27.5.61 |
| 0x363 | USBLPMIM | USB LPM Interrupt Mask | Section 27.5.62 |
| 0x364 | USBLPMRIS | USB LPM Raw Interrupt Status | Section 27.5.63 |
| 0x365 | USBLPMFADDR | USB LPM Function Address | Section 27.5.64 |
| 0x400 | USBEPC | USB External Power Control | Section 27.5.65 |
| 0x404 | USBEPCRIS | USB External Power Control Raw Interrupt Status | Section 27.5.66 |
| 0x408 | USBEPCIM | USB External Power Control Interrupt Mask | Section 27.5.67 |
| 0x40C | USBEPCISC | USB External Power Control Interrupt Status and Clear | Section 27.5.68 |
| 0x410 | USBDRRIS | USB Device RESUME Raw Interrupt Status | Section 27.5.69 |
| 0x414 | USBDRIM | USB Device RESUME Interrupt Mask | Section 27.5.70 |
| 0x418 | USBDRISC | USB Device RESUME Interrupt Status and Clear | Section 27.5.71 |
| 0x41C | USBGPCS | USB General-Purpose Control and Status | Section 27.5.72 |
| 0x430 | USBVDC | USB VBUS Droop Control | Section 27.5.73 |
| 0x434 | USBVDCRIS | USB VBUS Droop Control Raw Interrupt Status | Section 27.5.74 |
| 0x438 | USBVDCIM | USB VBUS Droop Control Interrupt Mask | Section 27.5.75 |
| 0x43C | USBVDCISC | USB VBUS Droop Control Interrupt Status and Clear | Section 27.5.76 |
| 0xFC0 | USBPP | USB Peripheral Properties | Section 27.5.77 |
| 0xFC4 | USBPC | USB Peripheral Configuration | Section 27.5.78 |
| 0xFC8 | USBCC | USB Clock Configuration | Section 27.5.79 |
Complex bit access types are encoded to fit into small table cells. Table 27-6 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W0 | W | Write |
| W1C | 1C
W |
1 to clear
Write |
| W1S | 1S
W |
1 to set
Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |