SLAU723A October 2017 ā October 2018 MSP432E401Y , MSP432E411Y
Table 19-3 lists the memory-mapped registers for the I2C. All register offset addresses not listed in Table 19-3 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0x0 | I2CMSA | I2C Master Slave Address | Section 19.5.1 |
| 0x4 | I2CMCS | I2C Master Control/Status | Section 19.5.2 |
| 0x8 | I2CMDR | I2C Master Data | Section 19.5.3 |
| 0xC | I2CMTPR | I2C Master Timer Period | Section 19.5.4 |
| 0x10 | I2CMIMR | I2C Master Interrupt Mask | Section 19.5.5 |
| 0x14 | I2CMRIS | I2C Master Raw Interrupt Status | Section 19.5.6 |
| 0x18 | I2CMMIS | I2C Master Masked Interrupt Status | Section 19.5.7 |
| 0x1C | I2CMICR | I2C Master Interrupt Clear | Section 19.5.8 |
| 0x20 | I2CMCR | I2C Master Configuration | Section 19.5.9 |
| 0x24 | I2CMCLKOCNT | I2C Master Clock Low Time-out Count | Section 19.5.10 |
| 0x2C | I2CMBMON | I2C Master Bus Monitor | Section 19.5.11 |
| 0x30 | I2CMBLEN | I2C Master Burst Length | Section 19.5.12 |
| 0x34 | I2CMBCNT | I2C Master Burst Count | Section 19.5.13 |
| 0x800 | I2CSOAR | I2C Slave Own Address | Section 19.5.14 |
| 0x804 | I2CSCSR | I2C Slave Control/Status | Section 19.5.15 |
| 0x808 | I2CSDR | I2C Slave Data | Section 19.5.16 |
| 0x80C | I2CSIMR | I2C Slave Interrupt Mask | Section 19.5.17 |
| 0x810 | I2CSRIS | I2C Slave Raw Interrupt Status | Section 19.5.18 |
| 0x814 | I2CSMIS | I2C Slave Masked Interrupt Status | Section 19.5.19 |
| 0x818 | I2CSICR | I2C Slave Interrupt Clear | Section 19.5.20 |
| 0x81C | I2CSOAR2 | I2C Slave Own Address 2 | Section 19.5.21 |
| 0x820 | I2CSACKCTL | I2C Slave ACK Control | Section 19.5.22 |
| 0xF00 | I2CFIFODATA | I2C FIFO Data | Section 19.5.23 |
| 0xF04 | I2CFIFOCTL | I2C FIFO Control | Section 19.5.24 |
| 0xF08 | I2CFIFOSTATUS | I2C FIFO Status | Section 19.5.25 |
| 0xFC0 | I2CPP | I2C Peripheral Properties | Section 19.5.26 |
| 0xFC4 | I2CPC | I2C Peripheral Configuration | Section 19.5.27 |
Complex bit access types are encoded to fit into small table cells. Table 19-4 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| RC | C
R |
to Clear
Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |