16.4.4 General-Purpose Mode
The General-Purpose Mode Configuration (EPIGPCFG) register is used to configure the control, data, and address pins, if used. Any unused EPI controller signals can be used as GPIOs or another alternate function. The general-purpose configuration can be used for custom interfaces with FPGAs, CPLDs, and digital data acquisition and actuator control.
General-Purpose mode is designed for three general types of use:
- Extremely high-speed clocked interfaces to FPGAs and CPLDs. Three sizes of data and optional address are supported. Framing and clock-enable functions permit more optimized interfaces.
- General parallel GPIO. From 1 to 32 pins may be written or read, with the speed precisely controlled by the EPIBAUD register baud rate (when used with the WFIFO and/or the NBRFIFO) or by the rate of accesses from software or µDMA. Examples of this type of use include:
- Reading 20 sensors at fixed time periods by configuring 20 pins to be inputs, configuring the COUNT0 field in the EPIBAUD register to some divider, and then using nonblocking reads.
- Implementing a very wide ganged PWM/PCM with fixed frequency for driving actuators or LEDs.
- General custom interfaces of any speed.
The configuration allows for choice of an output clock (free-running or gated), a framing signal (with frame size), a ready input (to stretch transactions), an address (of varying sizes), and data (of varying sizes). Additionally, provisions are made for separating data and address phases.
The interface has the following optional features:
- Use of the EPI clock output is controlled by the CLKPIN bit in the EPIGPCFG register. Unclocked uses include general-purpose I/O and asynchronous interfaces (optionally using RD and WR strobes). Clocked interfaces allow for higher speeds and are much easier to connect to FPGAs and CPLDs (which usually include input clocks).
- EPI clock, if used, may be free running or gated depending on the CLKGATE bit in the EPIGPCFG register. A free-running EPI clock requires another method for determining when data is live, such as the frame pin or RD/WR strobes. A gated clock approach uses a setup-time model in which the EPI clock controls when transactions are starting and stopping. The gated clock is held high until a new transaction is started and goes high at the end of the cycle where RD/WR/FRAME and address (and data if write) are emitted.
- Use of the RD and WR outputs is controlled by the RW bit in the EPIGPCFG register. For interfaces where the direction is known (in advance, related to frame size, or other means), these strobes are not needed. For most other interfaces, RD and WR are used so the external peripheral knows what transaction is taking place, and if any transaction is taking place.
- Separation of address/request and data phases may be used on writes using the WR2CYC bit in the EPIGPCFG register. This configuration allows the external peripheral extra time to act. Address and data phases must be separated on reads. When configured to use an address as specified by the ASIZE field in the EPIGPCFG register, the address is emitted on the with the RD strobe (first cycle) and data is expected to be returned on the next cycle (when RD is not asserted). If no address is used, then RD is asserted on the first cycle and data is captured on the second cycle (when RD is not asserted), allowing more setup time for data.
NOTE
When WR2CYC = 0, write data is valid when the WR strobe is asserted (High). When WR2CYC = 1, write data is valid when the WR strobe is Low after being asserted (High).
For writes, the output may be in one or two cycles. In the two-cycle case, the address (if any) is emitted on the first cycle with the WR strobe and the data is emitted on the second cycle (with WR not asserted). Although split address and write data phases are not normally needed for logic reasons, it may be useful to make read and write timings match. If 2-cycle reads or writes are used, the RW bit is automatically set.
- Address may be emitted (controlled by the ASIZE field in the EPIGPCFG register). The address may be up to 4 bits (16 possible values), up to 12 bits (4096 possible values), or up to 20 bits (1 M possible values). Size of address limits size of data, for example, 4 bits of address support up to 24 bits data. 4-bit address uses EPI0S[27:24]; 12-bit address uses EPI0S[27:16]; 20-bit address uses EPI0S[27:8]. The address signals may be used by the external peripheral as an address, code (command), or for other unrelated uses (such as a chip enable). If the chosen address/data combination does not use all of the EPI signals, the unused pins can be used as GPIOs or for other functions. For example, when using a 4-bit address with an 8-bit data, the pins assigned to EPIS0[23:8] can be assigned to other functions.
- Data may be 8 bits, 16 bits, 24 bits, or 32 bits (controlled by the DSIZE field in the EPIGPCFG register). By default, the EPI controller uses data bits [7:0] when the DSIZE field in the EPIGPCFG register is 0x0; data bits [15:0] when the DSIZE field is 0x1; data bits [23:0] when the DSIZE field is 0x2; and data bits [31:0] when the DSIZE field is 0x3.32-bit data cannot be used with address or EPI clock or any other signal. 24-bit data can only be used with 4-bit address or no address.
- When using the EPI controller as a GPIO interface, writes are FIFOed (up to 4 can be held at any time), and up to 32 pins are changed using the EPIBAUD clock rate specified by COUNT0. As a result, output pin control can be very precisely controlled as a function of time. By contrast, when writing to normal GPIOs, writes can only occur 8-bits at a time and take up to two clock cycles to complete. In addition, the write itself may be further delayed by the bus due to µDMA or draining of a previous write. With both GPIO and the EPI controller, reads may be performed directly, in which case the current pin states are read back. With the EPI controller, the nonblocking interface may also be used to perform reads based on a fixed time rule via the EPIBAUD clock rate.
Table 16-11 shows how the EPI0S[31:0] signals function while in General-Purpose mode. Notice that the address connections vary depending on the data-width restrictions of the external peripheral.
Table 16-11 EPI General-Purpose Signal Connections
| EPI Signal |
General-Purpose Signal (D8, A20) |
General-Purpose Signal (D16, A12) |
General-Purpose Signal (D24, A4) |
General-Purpose Signal (D32) |
| EPI0S0 |
D0 |
D0 |
D0 |
D0 |
| EPI0S1 |
D1 |
D1 |
D1 |
D1 |
| EPI0S2 |
D2 |
D2 |
D2 |
D2 |
| EPI0S3 |
D3 |
D3 |
D3 |
D3 |
| EPI0S4 |
D4 |
D4 |
D4 |
D4 |
| EPI0S5 |
D5 |
D5 |
D5 |
D5 |
| EPI0S6 |
D6 |
D6 |
D6 |
D6 |
| EPI0S7 |
D7 |
D7 |
D7 |
D7 |
| EPI0S8 |
A0 |
D8 |
D8 |
D8 |
| EPI0S9 |
A1 |
D9 |
D9 |
D9 |
| EPI0S10 |
A2 |
D10 |
D10 |
D10 |
| EPI0S11 |
A3 |
D11 |
D11 |
D11 |
| EPI0S12 |
A4 |
D12 |
D12 |
D12 |
| EPI0S13 |
A5 |
D13 |
D13 |
D13 |
| EPI0S14 |
A6 |
D14 |
D14 |
D14 |
| EPI0S15 |
A7 |
D15 |
D15 |
D15 |
| EPI0S16 |
A8 |
A0 (1) |
D16 |
D16 |
| EPI0S17 |
A9 |
A1 |
D17 |
D17 |
| EPI0S18 |
A10 |
A2 |
D18 |
D18 |
| EPI0S19 |
A11 |
A3 |
D19 |
D19 |
| EPI0S20 |
A12 |
A4 |
D20 |
D20 |
| EPI0S21 |
A13 |
A5 |
D21 |
D21 |
| EPI0S22 |
A14 |
A6 |
D22 |
D22 |
| EPI0S23 |
A15 |
A7 |
D23 |
D23 |
| EPI0S24 |
A16 |
A8 |
A0 (2) |
D24 |
| EPI0S25 |
A17 |
A9 |
A1 |
D25 |
| EPI0S26 |
A18 |
A10 |
A2 |
D26 |
| EPI0S27 |
A19 |
A11 |
A3 |
D27 |
| EPI0S28 |
WR |
WR |
WR |
D28 |
| EPI0S29 |
RD |
RD |
RD |
D29 |
| EPI0S30 |
Frame |
Frame |
Frame |
D30 |
| EPI0S31 |
Clock |
Clock |
Clock |
D31 |
(1) In this mode, halfword accesses are used. AO is the LSB of the address and is equivalent to the system A1 address.
(2) In this mode, word accesses are used. AO is the LSB of the address and is equivalent to the system A2 address.