2.5.6 SYSCTRL Register (Offset = 0xD10) [reset = 0x0]
System Control (SYSCTRL)
NOTE
This register can only be accessed from privileged mode.
The SYSCTRL register controls features of entry to and exit from low-power state.
SYSCTRL is shown in Figure 2-18 and described in Table 2-31.
Return to Summary Table.
Figure 2-18 SYSCTRL Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
SEVONPEND |
RESERVED |
SLEEPDEEP |
SLEEPEXIT |
RESERVED |
| R-0x0 |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
R/W-0x0 |
R-0x0 |
|
Table 2-31 SYSCTRL Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-5 |
RESERVED |
R |
0x0 |
|
| 4 |
SEVONPEND |
R/W |
0x0 |
Wake Up on Pending
When an event or interrupt enters the pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of a SEV instruction or an external event.
|
| 3 |
RESERVED |
R |
0x0 |
|
| 2 |
SLEEPDEEP |
R/W |
0x0 |
Deep Sleep Enable
|
| 1 |
SLEEPEXIT |
R/W |
0x0 |
Sleep on ISR Exit
Setting this bit enables an interrupt-driven application to avoid returning to an empty main application.
|
| 0 |
RESERVED |
R |
0x0 |
|