15.6.72 EPHYIM Register (Offset = 0xFD4) [reset = 0x0]
Ethernet PHY Interrupt Mask (EPHYIM)
The Ethernet PHY Interrupt Mask (EPHYIM) register is used to mask the interrupt from the Ethernet PHY, which is either from the internal integrated PHY or an external PHY.
EPHYIM is shown in Figure 15-87 and described in Table 15-97.
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Figure 15-87 EPHYIM Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
INT |
| R-0x0 |
R/W-0x0 |
|
Table 15-97 EPHYIM Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-1 |
RESERVED |
R |
0x0 |
|
| 0 |
INT |
R/W |
0x0 |
Ethernet PHY Interrupt Mask.
0x0 = An Ethernet PHY interrupt is suppressed and not sent to the interrupt controller.
0x1 = An Ethernet PHY interrupt is sent to the interrupt controller when the INT bit is set in the EPHYRIS register.This interrupt could be generated from either the integrated PHY or an external PHY through the EN0INTR signal depending on the configuration chosen.
|