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15.3.3.5.2 Enhanced Receive Descriptor
The DMA requires at least two descriptors when receiving a frame. The DMA always attempts to acquire an extra descriptor in anticipation of an incoming frame. Before the DMA closes a descriptor, it attempts to acquire the next descriptor even if no frames are received. In a single descriptor (receive) system, the subsystem generates a descriptor error if the receive buffer is unable to accommodate the incoming frame and the next descriptor is not owned by the DMA. Figure 15-6 shows the enhanced receive descriptor. This descriptor is used when Advanced Timestamp or the Checksum Offload Engine is enabled.
NOTE
When the Advanced Timestamp or Checksum Offload Engine features are enabled, software should set the ATDS bit of the Ethernet MAC DMA Bus Mode (EMACDMABUSMOD) register, offset 0xC00, so that the DMA operates with extended descriptor size. When this control bit is reset to the default (0), the TDES4-TDES7 descriptor space is not valid and only Alternate Descriptors are available, with a default size of 16 bytes (4 words).
Figure 15-6 Enhanced Receive Descriptor Structure The following tables define the Enhanced Receive Descriptors. RDES0 contains the received frame status, the frame length, and the descriptor ownership information (see Table 15-8). RDES1 contains the buffer sizes and other bits that control the descriptor chain or ring (see Table 15-10). RDES2 and RDES3 contains the address pointers to the first and second data buffers in the descriptor (see Table 15-11 and Table 15-12). The availability of the extended status is indicated by Bit 0 of RDES0. RDES6 and RDES7 are available only when the Advanced Timestamp or IP Checksum Full Offload feature is enabled (see Table 15-14 and Table 15-15).
Table 15-8 Enhanced Receive Descriptor 0 (RDES0)
| Bit | Description |
|---|---|
| 31 |
OWN: Own Bit When set, this bit indicates that the descriptor is owned by the DMA. When this bit is reset, it indicates that the descriptor is owned by the Host. The DMA clears this bit either when it completes the frame reception or when the buffers that are associated with this descriptor are full. |
| 30 |
AFM: Destination Address Filter Fail When set, this bit indicates a frame failed in the DA filter in the MAC. |
| 29:16 |
FL: Frame Length These bits indicate the byte length of the received frame that was transferred to the system memory. This field is valid when the Last Descriptor (RDES0[8]) is set and either the Descriptor Error (RDES0[14]) or the Overflow Error bit (RDES0[11]) is clear. When the Last Descriptor bit is not set, this field indicates the accumulated number of bytes that have been transferred for the current frame. The inclusion of CRC length in the frame length depends on the settings of CRC configuration bits, ACS and CST in the EMACCFG register. |
| 15 |
ES: Error Summary Indicates the logical OR of the following bits:
This field is valid only when the Last Descriptor (RDES0[8]) is set. |
| 14 |
DE: Descriptor Error When set, this bit indicates a frame truncation caused by a frame that does not fit within the current descriptor buffers, and that the DMA does not own the Next Descriptor. The frame is truncated. This field is valid only when the Last Descriptor (RDES0[8]) is set. |
| 13 |
SAF: Source Address Filter Fail When set, this bit indicates that the SA field of frame failed the SA Filter in the MAC. |
| 12 |
LE: Length Error When set, this bit indicates that the actual length of the frame received and the Length/Type field do not match. This bit is valid only when the Frame Type (RDES0[5]) bit is reset. Length error status is not valid when CRC error is present. |
| 11 |
OE: Overflow Error When set, this bit indicates that the received frame is damaged because of buffer overflow in RX FIFO. NOTE This bit is set only when the DMA transfers a partial frame to the application. This happens only when the RX FIFO is operating in the threshold mode. In the store-and-forward mode, all partial frames are dropped completely in RX FIFO. |
| 10 |
VLAN: VLAN Tag When set, this bit indicates that the frame pointed to by this descriptor is a VLAN frame tagged by the MAC. The VLAN tagging depends on checking VLAN fields of the received frame configured in the Ethernet MAC VLAN Tag (EMACVLANTG) register, offset 0x01C |
| 9 |
FS: First Descriptor When set, this bit indicates that this descriptor contains the first buffer of the frame. If the size of the first buffer is 0, the second buffer contains the beginning of the frame. If the size of the second buffer is also 0, the next Descriptor contains the beginning of the frame. |
| 8 |
LS: Last Descriptor When set, this bit indicates that the buffers pointed to by this descriptor are the last buffers of the frame. |
| 7 |
Timestamp Available or Giant Frame When Advanced Timestamp feature is enabled, this bit indicates that a snapshot of the Timestamp is written in descriptor words 6 (RDES6) and 7 (RDES7). This is valid only when the Last Descriptor bit (RDES0[8]) is set. Otherwise, this bit, when set, indicates the Giant Frame Status. Giant frames are larger than 1518-byte (or 1522-byte for VLAN or 2000-byte when Bit 27 of MAC Configuration register is set) normal frames and larger than 9018-byte (9022-byte for VLAN) frame when Jumbo Frame processing is enabled. |
| 6 |
LC: Late Collision When set, this bit indicates that a late collision has occurred while receiving the frame in half-duplex mode. |
| 5 |
FT: Frame Type When set, this bit indicates that the Receive Frame is an Ethernet-type frame (the LT field is greater than or equal to 1536). When this bit is reset, it indicates that the received frame is an IEEE 802.3 frame. This bit is not valid for Runt frames less than 14 bytes. In addition when the IPC bit is set in the EMACCFG register, this bit conveys different information. See Table 15-9. |
| 4 |
RWT: Receive Watchdog Timeout When set, this bit indicates that the Receive Watchdog Timer has expired while receiving the current frame and the current frame is truncated after the Watchdog Timeout. |
| 3 |
RE: Receive Error When set, this bit indicates that an error occurred during frame reception. |
| 2 |
DE: Dribble Bit Error When set, this bit indicates that the received frame has a non-integer multiple of bytes (odd nibbles). This bit is valid only in MII Mode. |
| 1 |
CE: CRC Error When set, this bit indicates that a Cyclic Redundancy Check (CRC) Error occurred on the received frame. This field is valid only when the Last Descriptor bit (RDES0[8]) is set. |
| 0 |
Extended Status Available/RX MAC Address When set, this bit indicates that the extended status is available in descriptor word 4 (RDES4). This is valid only when the Last Descriptor bit (RDES0[8]) is set. This bit is invalid when Bit 30 is set. |
Table 15-9 lists the frame information conveyed in bits 7, 5, and 0 of RDES0 when the Checksum Offload Engine is enabled and disabled through the IPC bit in the EMACCFG register.
Table 15-9 RDES0 Checksum Offload Bits
| Bit 5: Frame Type | Bit 7: IPC Checksum Error | Bit 0: Payload Checksum Error | IPC Bit Value in EMACCFG Register | Frame Status |
|---|---|---|---|---|
| 0 | 0 | 0 | X | IEEE 802.3 Type frame (Length field value is less than 1536). This status definition is valid even when the Checksum Offload engine is disabled. |
| 1 | 0 | 0 | 0 | IPv4/IPv6 Type frame in which no checksum error is detected. |
| 1 | 0 | 0 | 1 | The frame is an IEEE 802.3 Type frame (Length field value is greater than or equal to 1536). |
| 1 | 0 | 1 | 1 | IPv4/IPv6 Type frame with a payload checksum error detected |
| 1 | 1 | 1 | 1 | IPv4/IPv6 Type frame with both IP header and payload checksum errors detected |
| 0 | 0 | 1 | 1 | IPv4/IPv6 Type frame with no IP header checksum error and the payload check bypassed, due to an unsupported payload |
| 0 | 1 | 1 | 1 | A Type frame that is neither IPv4 or IPv6 (the Checksum Offload engine bypasses checksum completely.) |
| 0 | 1 | 0 | X | Reserved |
Table 15-10 Enhanced Receive Descriptor 1 (RDES1)
| Bit | Description |
|---|---|
| 31 |
Disable Interrupt on Completion When set, this bit prevents the setting of the Receive Interrupt (RI) bit in the EMACDMARIS register and prevents the receive interrupt from being asserted. |
| 30:29 |
Reserved |
| 28:16 |
RBS2: Receive Buffer 2 Size These bits indicate the second data buffer size. The buffer size must be a multiple of 4, even if the value of RDES3 (buffer 2 address pointer) is not aligned to the bus width. When the buffer size is not a multiple of 4, the resulting behavior is undefined. This field is not valid if RCH bit (RDES1[14]) is set. |
| 15 |
RER: Receive End of Ring When set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns to the base address of the list, creating a Descriptor Ring. |
| 14 |
RCH: Second Address Chained When set, this bit indicates that the second address in the descriptor is the Next Descriptor address rather than the second buffer address. When this bit is set, RBS2 (RDES1[28:16]) is a "don't care" value. RDES1[15] takes precedence over RDES1[14]. |
| 13 | Reserved |
| 12:0 |
RBS1: Receive Buffer 1 Size These bits indicate the first data buffer size in bytes. The buffer size must be a multiple of 4 even if the value of RDES2 (buffer 1 address pointer) is not aligned to the bus width. When the buffer size is not a multiple of 4, the resulting behavior is undefined. If this field is 0, the DMA ignores this buffer and uses Buffer 2 or the next descriptor depending on the value of RCH (Bit 14). |
Table 15-11 Enhanced Receive Descriptor 2 (RDES2)
| Bit | Description |
|---|---|
| 31:0 |
Buffer 1 Address Pointer These bits indicate the physical address of Buffer 1. The DMA uses the configured value for its address generation when the RDES2 value is used to store the start of frame. The DMA performs a write operation with the RDES2[1:0] bits as 0 during the transfer of the start of frame but the frame data is shifted as per the actual Buffer address pointer. The DMA ignores RDES2[1:0] if the address pointer is to a buffer where the middle or last part of the frame is stored. Note that buffers should be word-aligned. |
Table 15-12 Enhanced Receive Descriptor 3 (RDES3)
| Bit | Description |
|---|---|
| 31:0 |
Buffer 2 Address Pointer (Next Descriptor Address) These bits indicate the physical address of Buffer 2 when a descriptor ring structure is used. If the Second Address Chained (RDES1[14]) bit is set, this address contains the pointer to the physical memory where the Next Descriptor is present. If RDES1[14] is set, the buffer (Next Descriptor) address pointer must be bus word-aligned (RDES3[1:0] = 0) However, when RDES1[14] is reset, there are no limitations on the RDES3 value, except for the following condition: The DMA uses the configured value for its buffer address generation when the RDES3 value is used to store the start of frame. The DMA ignores RDES3 [1:0] if the address pointer is to a buffer where the middle or last part of the frame is stored. |
Table 15-13 Enhanced Received Descriptor 4 (RDES4)
| Bit | Description |
|---|---|
| 31:15 | Reserved |
| 14 | Timestamp Dropped
When set, this bit indicates that the timestamp was captured for this frame but got dropped in the RX FIFO because of overflow. |
| 13 | PTP Version
When set, this bit indicates that the received PTP message uses the IEEE 1588 version 2 format. When reset, it uses the version 1 format. |
| 12 | PTP Frame Type
When set, this bit indicates that the PTP message is sent directly over Ethernet. When this bit is clear and the message type is non-zero, it indicates that the PTP message is sent over UDP-IPv4 or UDP-IPv6. The information about IPv4 or IPv6 can be obtained from Bits 6 and 7. |
| 11:8 | Message Type
These bits are encoded to give the type of the message received:
|
| 7 | IPv6 Packet Received
When set, this bit indicates that the received packet is an IPv6 packet. This bit is updated only when the IPC bit of the EMACCFG register is set. |
| 6 | IPv4 Packet Received
When set, this bit indicates that the received packet is an IPv4 packet. This bit is updated only when the IPC bit of the EMACCFG register is set. |
| 5 | IP Checksum Bypassed
When set, this bit indicates that the checksum offload engine is bypassed. |
| 4 | IP Payload Error
When set, this bit indicates that the 16-bit IP payload checksum (that is, the TCP, UDP, or ICMP checksum) that the core calculated does not match the corresponding checksum field in the received segment. It is also set when the TCP, UDP, or ICMP segment length does not match the payload length value in the IP Header field. This bit is valid when either Bit 7 or Bit 6 is set. |
| 3 | IP Header Error
When set, this bit indicates that either the 16-bit IPv4 header checksum calculated by the core does not match the received checksum bytes, or the IP datagram version is not consistent with the Ethernet Type value. This bit is valid when either Bit 7 or Bit 6 is set. |
| 2:0 | IP Payload Type
These bits indicate the type of payload encapsulated in the IP datagram processed by the Receive Checksum Offload Engine (COE). The COE sets this field to 0x0 if it does not process the IP datagram's payload due to an IP header error or fragmented IP packet.
This bit is valid when either Bit 7 or Bit 6 is set. |
Table 15-14 Enhanced Receive Descriptor 6 (RDES6)
| Bit | Description |
|---|---|
| 31:0 | RTSL: Receive Frame Timestamp Low
This field is updated by the DMA with the least significant 32 bits of the timestamp captured for the corresponding receive frame. This field is updated by the DMA only for the last descriptor of the receive frame which is indicated by Last Descriptor status bit (RDES0[8]). |
Table 15-15 Enhanced Receive Descriptor 7 (RDES7)
| Bit | Description |
|---|---|
| 31:0 | RTSH: Receive Frame Timestamp High
This field is updated by DMA with the most significant 32 bits of the timestamp captured for the corresponding receive frame. This field is updated by DMA only for the last descriptor of the receive frame which is indicated by Last Descriptor status bit (RDES0[8]). |