SLAU723A October 2017 ā October 2018 MSP432E401Y , MSP432E411Y
A basic access is 1 EPI clock for write cycles and 2 EPI clock cycles for read cycles. An additional EPI clock can be inserted into a write cycle by setting the WR2CYC bit in the EPIGPCFG register.
Figure 16-19 Single-Cycle Single Write Access, FRM50 = 0, FRMCNT = 0, WR2CYC = 0
Figure 16-20 Two-Cycle Read, Write Accesses, FRM50 = 0, FRMCNT = 0, WR2CYC = 1
Figure 16-21 Read Accesses, FRM50 = 0, FRMCNT = 0