15.5 Initialization and Configuration
The MAC module and registers are enabled and powered at reset. When reset has completed, the application should enable the clock to the Ethernet MAC by setting the R0 bit in the Ethernet Controller Run Mode Clock Gating Control (RCGCEMAC) register at System Control Module offset 0x69C. When the PREMAC register, at System Control offset 0xA9C reads as 0x0000.0001, the EMAC registers are ready to be accessed.
The EMAC interface defaults to MII mode. If RMII mode is required, follow these steps:
- Enable the external clock source input to the RMII interface signal EN0RREF_CLK by setting both the ECEXT and CLKEN bit in the in the Ethernet Clock Configuration (EMACCC) register at offset 0xFC8. The external clock source must be 50 MHz with a frequency tolerance of 50 PPM.
- Select the RMII interface by programming the PINTFS bit field to 0x4 in the Ethernet Peripheral Configuration (EMACPC) register at offset 0xFC4.
- Reset the Ethernet MAC to latch the new RMII configuration by setting the SWR bit in the EMACDMABUSMOD register. This bit resets the Ethernet MAC registers in addition to configuring the RMII interface. Software must poll the SWR bit to determine when the new configuration has been registered.
NOTE
After this configuration is active, if the Ethernet MAC is reset by setting the R0 bit in the Ethernet MAC Software Reset (SREMAC) register in the System Control Module, then the interface is set back to its default MII configuration. In this case, the steps listed above must be repeated to return to an RMII interface.
The Initialization for the DMA for the Ethernet MAC is as follows:
- Write to the Ethernet MAC DMA Bus Mode (EMACDMABUSMOD) register to set Host bus parameters.
- Write to the Ethernet MAC DMA Interrupt Mask Register (EMACDMAIM) register to mask unnecessary interrupt causes.
- Create the transmit and receive descriptor lists and then write to the Ethernet MAC Receive Descriptor List Address (EMACRXDLADDR) register and the Ethernet MAC Transmit Descriptor List Address (EMACTXDLADDR) register providing the DMA with the starting address of each list.
- Write to the Ethernet MAC Frame Filter (EMACFRAMEFLTR) register, the Ethernet MAC Hash Table High (EMACHASHTBLH) and the Ethernet MAC Hash Table Low (EMACHASHTBLL) for desired filtering options.
- Write to the Ethernet MAC Configuration Register (EMACCFG) to configure the operating mode and enable the transmit operation.
- Program Bit 15 (PS) and Bit 11 (DM) of the EMACCFG register based on the line status received or read from the PHY status register after auto-negotiation.
- Write to the Ethernet MAC DMA Operation Mode (EMACDMAOPMODE) register to set Bits 13 and 1 to start transmission and reception.
- Write to the EMACCFG register to enable the receive operation.
The Transmit and Receive engines enter the Running state and attempt to acquire descriptors from the respective descriptor lists. The Receive and Transmit engines then begin processing Receive and Transmit operations. The Transmit and Receive processes are independent of each other and can be started or stopped separately.