15.6.41 EMACSUBSECINC Register (Offset = 0x704) [reset = 0x0]
Ethernet MAC Sub-Second Increment (EMACSUBSECINC)
In the Coarse Update mode (enabled by the TSCFUPDT bit in the MAC Timestamp Control (EMACTIMSTCTRL) register), the value in the EMACSUBSECINC register is added to the system time every clock cycle of slave clock reference, MOSC. In the Fine Update mode, the value in this register is added to the system time whenever the Accumulator gets an overflow.
EMACSUBSECINC is shown in Figure 15-56 and described in Table 15-65.
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Figure 15-56 EMACSUBSECINC Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
SSINC |
| R-0x0 |
R/W-0x0 |
|
Table 15-65 EMACSUBSECINC Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-8 |
RESERVED |
R |
0x0 |
|
| 7-0 |
SSINC |
R/W |
0x0 |
Sub-second Increment Value. The value programmed in this field is accumulated every clock cycle (MOSC) with the contents of the sub-second register. For example, when MOSC is 25 MHz (period is 40 ns), SSINC should be programmed with the value 40 (0x28) when the Ethernet MAC System Time - Nanoseconds (EMACTIMNANO) register has an accuracy of 1 ns (DGTLBIN bit is set in EMACTIMSTCTRL). When DGTLBIN bit is clear, the EMACTIMNANO register has a resolution of ~0.465ns. In this case, a value of 86 (0x56), that is derived by 40ns/0.465, should be programmed in the SSINC field.
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