SLAU723A October 2017 ā October 2018 MSP432E401Y , MSP432E411Y
Table 10-6 lists the memory-mapped registers for the ADC. All register offset addresses not listed in Table 10-6 should be considered as reserved locations and the register contents should not be modified.
The offset listed is relative to the base address of the ADC module:
The ADC module clock must be enabled before the registers can be programmed (see Section 4.2.97). There must be a delay of 3 system clock cycles after the ADC module clock is enabled before any ADC module registers are accessed.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0x0 | ADCACTSS | ADC Active Sample Sequencer | Section 10.5.1 |
| 0x4 | ADCRIS | ADC Raw Interrupt Status | Section 10.5.2 |
| 0x8 | ADCIM | ADC Interrupt Mask | Section 10.5.3 |
| 0xC | ADCISC | ADC Interrupt Status and Clear | Section 10.5.4 |
| 0x10 | ADCOSTAT | ADC Overflow Status | Section 10.5.5 |
| 0x14 | ADCEMUX | ADC Event Multiplexer Select | Section 10.5.6 |
| 0x18 | ADCUSTAT | ADC Underflow Status | Section 10.5.7 |
| 0x1C | ADCTSSEL | ADC Trigger Source Select | Section 10.5.8 |
| 0x20 | ADCSSPRI | ADC Sample Sequencer Priority | Section 10.5.9 |
| 0x24 | ADCSPC | ADC Sample Phase Control | Section 10.5.10 |
| 0x28 | ADCPSSI | ADC Processor Sample Sequence Initiate | Section 10.5.11 |
| 0x30 | ADCSAC | ADC Sample Averaging Control | Section 10.5.12 |
| 0x34 | ADCDCISC | ADC Digital Comparator Interrupt Status and Clear | Section 10.5.13 |
| 0x38 | ADCCTL | ADC Control | Section 10.5.14 |
| 0x40 | ADCSSMUX0 | ADC Sample Sequence Input Multiplexer Select 0 | Section 10.5.15 |
| 0x44 | ADCSSCTL0 | ADC Sample Sequence Control 0 | Section 10.5.16 |
| 0x48 | ADCSSFIFO0 | ADC Sample Sequence Result FIFO 0 | Section 10.5.17 |
| 0x4C | ADCSSFSTAT0 | ADC Sample Sequence FIFO 0 Status | Section 10.5.18 |
| 0x50 | ADCSSOP0 | ADC Sample Sequence 0 Operation | Section 10.5.19 |
| 0x54 | ADCSSDC0 | ADC Sample Sequence 0 Digital Comparator Select | Section 10.5.20 |
| 0x58 | ADCSSEMUX0 | ADC Sample Sequence Extended Input Multiplexer Select 0 | Section 10.5.21 |
| 0x5C | ADCSSTSH0 | ADC Sample Sequence 0 Sample and Hold Time | Section 10.5.22 |
| 0x60 | ADCSSMUX1 | ADC Sample Sequence Input Multiplexer Select 1 | Section 10.5.23 |
| 0x64 | ADCSSCTL1 | ADC Sample Sequence Control 1 | Section 10.5.24 |
| 0x068 | ADCSSFIFO1 | ADC Sample Sequence Result FIFO 1 | Section 10.5.17 |
| 0x06C | ADCSSFSTAT1 | ADC Sample Sequence FIFO 1 Status | Section 10.5.18 |
| 0x70 | ADCSSOP1 | ADC Sample Sequence 1 Operation | Section 10.5.25 |
| 0x74 | ADCSSDC1 | ADC Sample Sequence 1 Digital Comparator Select | Section 10.5.26 |
| 0x78 | ADCSSEMUX1 | ADC Sample Sequence Extended Input Multiplexer Select 1 | Section 10.5.27 |
| 0x7C | ADCSSTSH1 | ADC Sample Sequence 1 Sample and Hold Time | Section 10.5.28 |
| 0x080 | ADCSSMUX2 | ADC Sample Sequence Input Multiplexer Select 2 | Section 10.5.23 |
| 0x084 | ADCSSCTL2 | ADC Sample Sequence Control 2 | Section 10.5.24 |
| 0x088 | ADCSSFIFO2 | ADC Sample Sequence Result FIFO 2 | Section 10.5.17 |
| 0x08C | ADCSSFSTAT2 | ADC Sample Sequence FIFO 2 Status | Section 10.5.18 |
| 0x090 | ADCSSOP2 | ADC Sample Sequence 2 Operation | Section 10.5.25 |
| 0x094 | ADCSSDC2 | ADC Sample Sequence 2 Digital Comparator Select | Section 10.5.26 |
| 0x098 | ADCSSEMUX2 | ADC Sample Sequence Extended Input Multiplexer Select 2 | Section 10.5.27 |
| 0x09C | ADCSSTSH2 | ADC Sample Sequence 2 Sample and Hold Time | Section 10.5.28 |
| 0xA0 | ADCSSMUX3 | ADC Sample Sequence Input Multiplexer Select 3 | Section 10.5.29 |
| 0xA4 | ADCSSCTL3 | ADC Sample Sequence Control 3 | Section 10.5.30 |
| 0x0A8 | ADCSSFIFO3 | ADC Sample Sequence Result FIFO 3 | Section 10.5.17 |
| 0x0AC | ADCSSFSTAT3 | ADC Sample Sequence FIFO 3 Status | Section 10.5.18 |
| 0xB0 | ADCSSOP3 | ADC Sample Sequence 3 Operation | Section 10.5.31 |
| 0xB4 | ADCSSDC3 | ADC Sample Sequence 3 Digital Comparator Select | Section 10.5.32 |
| 0xB8 | ADCSSEMUX3 | ADC Sample Sequence Extended Input Multiplexer Select 3 | Section 10.5.33 |
| 0xBC | ADCSSTSH3 | ADC Sample Sequence 3 Sample and Hold Time | Section 10.5.34 |
| 0xD00 | ADCDCRIC | ADC Digital Comparator Reset Initial Conditions | Section 10.5.35 |
| 0xE00 to 0xE1C | ADCDCCTL0 to ADCDCCTL7 | ADC Digital Comparator Control 0 to ADC Digital Comparator Control 7 | Section 10.5.36 |
| 0xE40 to 0xE5C | ADCDCCMP0 to ADCDCCMP7 | ADC Digital Comparator Range 0 to ADC Digital Comparator Range 7 | Section 10.5.37 |
| 0xFC0 | ADCPP | ADC Peripheral Properties | Section 10.5.38 |
| 0xFC4 | ADCPC | ADC Peripheral Configuration | Section 10.5.39 |
| 0xFC8 | ADCCC | ADC Clock Configuration | Section 10.5.40 |
Complex bit access types are encoded to fit into small table cells. Table 10-7 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W1C | 1C
W |
1 to clear
Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |