SLAU723A October 2017 ā October 2018 MSP432E401Y , MSP432E411Y
All single-precision values with the maximum exponent field value and a nonzero fraction field are valid NaNs. A most-significant fraction bit of zero indicates a Signaling NaN (SNaN). A one indicates a Quiet NaN (QNaN). Two NaN values are treated as different NaNs if they differ in any bit. The table below shows the default NaN values.
| Sign | Fraction | Fraction |
|---|---|---|
| 0 | 0xFF | bit [22] = 1, bits [21:0] are all zeros |
Processing of input NaNs for Arm floating-point functionality and libraries is defined as follows:
| Instruction Type | Default NaN Mode | With QNaN Operand | With SNaN Operand |
|---|---|---|---|
| Arithmetic CDP | Off | The QNaN or one of the QNaN operands, if there is more than one, is returned according to the rules given in the | IOC(1) set. The SNaN is quieted and the result NaN is determined by the rules given in the Arm Architecture Reference Manual. |
| On | Default NaN returns. | IOC(1) set. Default NaN returns. | |
| Non-arithmetic CDP | Off/On | NaN passes to destination with sign changed as appropriate. | |
| FCMP(Z) | – | Unordered compare. | IOC set. Unordered compare. |
| FCMPE(Z) | – | IOC set. Unordered compare. | IOC set. Unordered compare. |
| All NaNs transferred | Off/On | All NaNs transferred | |