8.6.14 DMAALTCLR Register (Offset = 0x34) [reset = X]
DMA Channel Primary Alternate Clear (DMAALTCLR)
Each bit of the DMAALTCLR register represents the corresponding µDMA channel. Setting a bit clears the corresponding SET[n] bit in the DMAALTSET register.
DMAALTCLR is shown in Figure 8-23 and described in Table 8-33.
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Figure 8-23 DMAALTCLR Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| CLR[n] |
| W-X |
|
Table 8-33 DMAALTCLR Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-0 |
CLR[n] |
W |
X |
Channel [n] Alternate Clear
For Ping-Pong and Scatter-Gather cycle types, the µDMA controller automatically sets these bits to select the alternate channel control data structure.
0x0 = No effect.
0x1 = Setting a bit clears the corresponding SET[n] bit in the DMAALTSET register meaning that channel [n] is using the primary control structure.
|