27.5.51 USBDMACTLn Register [reset = 0x0]
USB DMA Control 0 (USBDMACTL0), offset 0x204
USB DMA Control 1 (USBDMACTL1), offset 0x214
USB DMA Control 2 (USBDMACTL2), offset 0x224
USB DMA Control 3 (USBDMACTL3), offset 0x234
USB DMA Control 4 (USBDMACTL4), offset 0x244
USB DMA Control 5 (USBDMACTL5), offset 0x254
USB DMA Control 6 (USBDMACTL6), offset 0x264
USB DMA Control 7 (USBDMACTL7), offset 0x274
OTG A / Host
OTG B / Device
This register provides the DMA transfer control for each channel. The enabling, transfer direction, transfer mode, the DMA burst modes are all controlled by this register.
USBDMACTLn is shown in Figure 27-62 and described in Table 27-69.
Return to Summary Table.
Figure 27-62 USBDMACTLn Register
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
BRSTM |
ERR |
| R-0x0 |
R-0x0 |
R/W-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| EP |
IE |
MODE |
DIR |
ENABLE |
| R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 27-69 USBDMACTLn Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 15-11 |
RESERVED |
R |
0x0 |
|
| 10-9 |
BRSTM |
R |
0x0 |
Burst Mode.
0x0 = Bursts of unspecified length
0x1 = INCR4 or unspecified length
0x2 = INCR8, INCR4 or unspecified length
0x3 = INCR16, INCR8, INCR4 or unspecified length
|
| 8 |
ERR |
R/W |
0x0 |
Bus Error Bit.
This bit is cleared by software.
0x0 = No effect
0x1 = A bus error has occurred.
|
| 7-4 |
EP |
R/W |
0x0 |
Endpoint number.
This field indicates the endpoint number to which this channel is assigned.
This value can be 0x1 to 0x7. |
| 3 |
IE |
R/W |
0x0 |
DMA Interrupt Enable.
0x0 = No effect
0x1 = Interrupt is enabled for this channel
|
| 2 |
MODE |
R/W |
0x0 |
DMA Transfer Mode.
0x0 = DMA Mode0 Transfer
0x1 = DMA Mode1 Transfer
|
| 1 |
DIR |
R/W |
0x0 |
DMA Direction.
0x0 = DMA Write (RX endpoint)
0x1 = DMA Read (TX Endpoint)
|
| 0 |
ENABLE |
R/W |
0x0 |
DMA Transfer Enable.
0x0 = No effect.
0x1 = DMA transfer is initiated.
|