19.5.27 I2CPC Register (Offset = 0xFC4) [reset = 0x1]
I2C Peripheral Configuration (I2CPC)
The I2CPC register allows software to enable features present in the I2C module.
I2CPC is shown in Figure 19-44 and described in Table 19-34.
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Figure 19-44 I2CPC Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x1 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
| R-0x1 |
|
Table 19-34 I2CPC Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 0 |
HS |
R/W |
0x1 |
High-Speed Capable
0x0 = The interface is set to Standard, Fast or Fast mode plus operation.
0x1 = The interface is set to High-Speed operation. Note that this encoding may only be used if the HS bit in the I2CPP register is set. Otherwise, this encoding is not available.
|
| 31-0 |
RESERVED |
R |
0x1 |
|