| 31-12 |
RESERVED |
R |
0x0 |
|
| 11 |
TBMADCEN |
R/W |
0x0 |
GPTM B Mode Match Event ADC Trigger Enable.
When this bit is enabled, a a trigger pulse is sent to the ADC when a mode match has occurred.
0x0 = Timer B Mode Match ADC trigger is disabled.
0x1 = Timer B Mode Match ADC trigger is enabled.
|
| 10 |
CBEADCEN |
R/W |
0x0 |
GPTM B Capture Event ADC Trigger Enable.
When this bit is enabled, a trigger pulse is sent to the ADC when a capture event has occurred.
0x0 = Timer B Capture Event ADC trigger is disabled.
0x1 = Timer B Capture Event ADC trigger is enabled.
|
| 9 |
CBMADCEN |
R/W |
0x0 |
GPTM B Capture Match Event ADC Trigger Enable.
When this bit is enabled, a trigger signal is sent to the ADC when a capture match event has occurred.
0x0 = Timer B Capture Match ADC trigger is disabled.
0x1 = Timer B Capture Match ADC trigger is enabled.
|
| 8 |
TBTOADCEN |
R/W |
0x0 |
GPTM B Time-Out Event ADC Trigger Enable.
When this bit is enabled, a trigger signal is sent to the ADC on a time-out event.
0x0 = Timer B Time-Out ADC trigger is disabled.
0x1 = Timer B Time-Out ADC trigger is enabled.
|
| 7-5 |
RESERVED |
R |
0x0 |
|
| 4 |
TAMADCEN |
R/W |
0x0 |
GPTM A Mode Match Event ADC Trigger Enable.
When this bit is enabled, a a trigger pulse is sent to the ADC when a mode match has occurred.
0x0 = Timer A Mode Match ADC trigger is disabled.
0x1 = Timer A Mode Match ADC trigger is enabled.
|
| 3 |
RTCADCEN |
R/W |
0x0 |
GPTM RTC Match Event ADC Trigger Enable.
When this bit is enabled, a trigger signal is sent to the ADC when a RTC match has occurred.
0x0 = Timer A RTC Match ADC trigger is disabled.
0x1 = Timer A RTC Match ADC trigger is enabled.
|
| 2 |
CAEADCEN |
R/W |
0x0 |
GPTM A Capture Event ADC Trigger Enable.
When this bit is enabled, a trigger pulse is sent to the ADC when a capture event has occurred.
0x0 = Timer A Capture Event ADC trigger is disabled.
0x1 = Timer A Capture Event ADC trigger is enabled.
|
| 1 |
CAMADCEN |
R/W |
0x0 |
GPTM A Capture Match Event ADC Trigger Enable.
When this bit is enabled, a trigger signal is sent to the ADC when a capture match event has occurred.
0x0 = Timer A Capture Match ADC trigger is disabled.
0x1 = Timer A Capture Match ADC trigger is enabled.
|
| 0 |
TATOADCEN |
R/W |
0x0 |
GPTM A Time-Out Event ADC Trigger Enable.
When this bit is enabled, a trigger signal is sent to the ADC on a time-out event.
0x0 = Timer A Time-Out Event ADC trigger is disabled.
0x1 = Timer A Time-Out Event ADC trigger is enabled.
|