| 31 |
N |
R/W |
X |
Negative Condition Code Flag Floating-point comparison operations update this condition code flag.
|
| 30 |
Z |
R/W |
X |
Zero Condition Code Flag Floating-point comparison operations update this condition code flag.
|
| 29 |
C |
R/W |
X |
Carry Condition Code Flag Floating-point comparison operations update this condition code flag.
|
| 28 |
V |
R/W |
X |
Overflow Condition Code Flag Floating-point comparison operations update this condition code flag.
|
| 27 |
RESERVED |
R |
0h |
|
| 26 |
AHP |
R/W |
X |
Alternative Half-Precision. When set, alternative half-precision format is selected. When clear, IEEE half-precision format is selected. The AHP bit in the FPDSC register holds the default value for this bit.
|
| 25 |
DN |
R/W |
X |
Default NaN Mode. When set, any operation involving one or more NaNs returns the Default NaN. When clear, NaN operands propagate through to the output of a floating-point operation. The DN bit in the FPDSC register holds the default value for this bit.
|
| 24 |
FZ |
R/W |
X |
Flush-to-Zero Mode. When set, Flush-to-Zero mode is enabled. When clear, Flush-to-Zero mode is disabled and the behavior of the floating-point system is fully compliant with the IEEE 754 standard. The FZ bit in the FPDSC register holds the default value for this bit.
|
| 23:22 |
RMODE |
R/W |
X |
Rounding Mode. The specified rounding mode is used by almost all floating-point instructions. The RMODE bit in the FPDSC register holds the default value for this bit.
|
| 21:8 |
RESERVED |
R |
0h |
|
| 7 |
IDC |
R/W |
X |
Input Denormal Cumulative Exception. When set, indicates this exception has occurred since 0 was last written to this bit.
|
| 6:5 |
RESERVED |
R |
0h |
|
| 4 |
IXC |
R/W |
X |
Inexact Cumulative Exception. When set, indicates this exception has occurred since 0 was last written to this bit.
|
| 3 |
UFC |
R/W |
X |
Underflow Cumulative Exception. When set, indicates this exception has occurred since 0 was last written to this bit.
|
| 2 |
OFC |
R/W |
X |
Overflow Cumulative Exception. When set, indicates this exception has occurred since 0 was last written to this bit.
|
| 1 |
DZC |
R/W |
X |
Division by Zero Cumulative Exception. When set, indicates this exception has occurred since 0 was last written to this bit.
|
| 0 |
IOC |
R/W |
X |
Invalid Operation Cumulative Exception. When set, indicates this exception has occurred since 0 was last written to this bit.
|