Integrated in MAIN domain: One
instance of the Programmable Real-Time Unit Subsystem used primarily for driving
GPIO for cycle accurate protocols such as additional UARTS, I2C and external
ADC.
MAIN domain encompasses one PRUSS
subsystem, supporting the following main features, among others:
- One Programmable Real-time
Unit Subsystem (PRUSS):
- 2 PRU cores (PRU0 and
PRU1):
- Asynchronous
capture (Serial Capture Unit (SCU)] with EnDat 2.2 protocol
and Sigma-Delta demodulation support
- 20 Enhanced
General Purpose Inputs (EGPI) and 20 Enhanced General
Purpose Outputs (EGPO)
- 12 KB program
memory per PRU (PRU0_IRAM and PRU1_IRAM) with ECC
- CRC16/CRC32
HW accelerator
- RX
XFR2VBUS
- Scratchpad Memory (SPAD) with
2 banks of 30 x 32-bit registers
- 3 banks for the PRU0
and PRU1 cores
- 32KB shared general purpose
RAM with ECC, shared between PRU0 and PRU1
- Two 8KB (shared) Data
Memories with ECC (one per slice)
- 36-bit VBUSM Controller Port
- Optional address
translation for all transactions to External Host
- 16 Software Events generated
by 2 PRUs
- One Enhanced Capture (ECAP)
module
- One interrupt controller
(INTC)
- Up to 32 internal
events, generated by modules, internal to the PRUSS
- Up to 32 external
events, generated by the system
- Supports up to 10
interrupt channels
- Generation of 18 Host
interrupts
- 2 Host
interrupts tp PRU0, PRU1
- 8 Host
interrupts, exported from the PRUSS for signaling the Arm
interrupt controllers (pulse and level provided)
- Each system event can
be enabled and disabled
- Each host event can
be enabled and disabled
- Hardware
prioritization of events
- One 32-bit VBUSP target port
for memory mapped register and internal memories access
- Flexible power management
support
- Integrated 32-bit
interconnect