SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
Figure 12-10 shows an asynchronous single-write operation on an AAD-multiplexed device.
Figure 12-181 Asynchronous Single Write on an AAD-Multiplexed DeviceFor formulas to calculate timing parameters, see Section 12.4.3.5.6.1, GPMC Timing Parameters Formulas.
Table 12-232 lists the timing bit fields to set up to configure the GPMC in asynchronous single-write mode.
When the GPMC generates a write access to an AAD-multiplexed device, all address bits are driven onto the address/data bus in two separate phases. The first phase is used for the MSB address and is qualified with nOE driven low. The second phase for LSB address is qualified with nOE driven high. The address phase ends at nWE assertion time.
The nCS, nWE, and DIR signals are controlled in the same way as for an asynchronous single-write operation on an address/data-multiplexed device. See Table 12-223, NAND Memory Type.
The address bits for the first address phase are driven onto the data bus until nOE deassertion. Data is driven onto the address/data bus at the clock edge defined by the GPMC_CONFIG6_i[19-16] WRDATAONADMUXBUS parameter.