SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
The PRUSS external interface signals are described in Table 7-28. The PRUSS has a large number of available I/O signals. Most of these are multiplexed with other functional signals at the device level.
The PRUSS also support an internal wrapper multiplexing that expands the device top-level multiplexing. This wrapper multiplexing is controlled by the GPCFGx_REG register (where x = 0 or 1) in the PRUSS CFG register space and allows MII_RT, 3 channel Peripheral Interface (with EnDAT capabilities), and Sigma Delta functionality to be muxed with the PRU GPI/O device signals, as shown in Figure 7-11. The PRUSS wrapper multiplexing is described with the device-level signals in Table 7-28. Note that the device top-level muxing has higher priority over the internal PRUSS muxing.
Additionally to PRUSS wrapper multiplexing the device I/O logic maps the PRUSS signals to the different device pins by programming the associated IOMUX CTRLMMR register.
Figure 7-12 PRU-ICSS External Interface I/Os