| MAILBOX0_CLUSTER_0 |
MAILBOX0_CLUSTER_0_mailbox_cluster_pend_0 |
GICSS0_spi_108 |
GICSS0 |
MAILBOX0_CLUSTER_0 interrupt request |
level |
| MAILBOX0_CLUSTER_0 |
MAILBOX0_CLUSTER_0_mailbox_cluster_pend_1 |
GICSS0_spi_109 |
GICSS0 |
MAILBOX0_CLUSTER_0 interrupt request |
level |
| MAILBOX0_CLUSTER_0 |
MAILBOX0_CLUSTER_0_mailbox_cluster_pend_1 |
WKUP_R5FSS0_CORE0_intr_254 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_CLUSTER_0 interrupt request |
level |
| MAILBOX0_CLUSTER_0 |
MAILBOX0_CLUSTER_0_mailbox_cluster_pend_2 |
MCU_M4FSS0_CORE0_nvic_50 |
MCU_M4FSS0_CORE0 |
MAILBOX0_CLUSTER_0 interrupt request |
level |
| MAILBOX0_CLUSTER_0 |
MAILBOX0_CLUSTER_0_mailbox_cluster_pend_3 |
WKUP_R5FSS0_CORE0_intr_255 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_CLUSTER_0 interrupt request |
level |