SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
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| Instance Name | Physical Address |
|---|---|
| CTRL_MMR0 | 0010 A060h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| MAIN_PLL0_CLKSEL_BYPASS_SW_OVRD_PROXY | RESERVED | ||||||
| R/W | NONE | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| MAIN_PLL0_CLKSEL_BYP_WARM_RST_PROXY | RESERVED | ||||||
| R/W | NONE | ||||||
| 1h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | MAIN_PLL0_CLKSEL_BYPASS_SW_OVRD_PROXY | R/W | 0h | PLL Bypass warm reset software override When set, activates software control of exit from bypass mode on a main_reset_z for MAIN PLL0. This bit must not be set until after the corresponding byp_warm_rst bit has been cleared or the PLL will immediately enter bypass mode. Reset Source: sys_por_rst_n |
| 30:24 | RESERVED | NONE | 0h | Reserved |
| 23 | MAIN_PLL0_CLKSEL_BYP_WARM_RST_PROXY | R/W | 1h | PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to activate bypass software override. This bit is set (1'b0) when a MAIN warm reset occurs to keep MAIN PLL0 from being bypassed, supporting reset isolation of the CPSW. 1'b0 = Exit bypass mode (based on MAIN PLL0_CTRL_bypass_en bit value) 1'b1 = Maintain bypass mode. Reset Source: main_chip1_rst_n |
| 22:0 | RESERVED | NONE | 0h | Reserved |