SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
During Deeplseep resume sequence if the Device Manager is unable to respond due to a software bug, the WKUP domain WDT timer will issue this reset signal.
When this reset is enabled in MCU domain, it causes a whole device warm reset.
This WKUP WDT reset is enabled only when the DM_WDT_RST_EN_z bit in MCU domain CTRLMMR is '0'.
When the M4FSS is configured as a safety processor, it can block this reset from resetting the MCU domain. This is an asynchronous reset type (takes effect immediately)
All modules in MCU domain are reset except for MCU domain CTRLMMR bits which are reset only on MCU_PORz.
IOs are not affected. M4FSS is reset.
When this reset is de-asserted, the MCU domain will be reconfigured by R5FSS (secondary boot loader) in the MAIN domain.
All modules in the MAIN domain are reset except for CTRLMMR bits which are reset only on PORz.
IOs are not affected.
All processor cores are reset (A53SS, SMS, and R5FSS).
When this reset is de-asserted, the device goes through full boot. The reason for this reset is captured inthe CTRLMMR reset source register.
During device boot-up, the R5FSS (secondary boot loader) will read the CTRLMMR reset status and MCU ACTIVE MAGIC WORD and reconfigure the MCU domain/M4FSS processor accordingly.