| MCSPI0 |
MCSPI0_dma_read_event_0 |
PDMA0_spi_main_0_rx_0 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_read_event_1 |
PDMA0_spi_main_0_rx_1 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_read_event_2 |
PDMA0_spi_main_0_rx_2 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_read_event_3 |
PDMA0_spi_main_0_rx_3 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_write_event_0 |
PDMA0_spi_main_0_tx_0 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_write_event_1 |
PDMA0_spi_main_0_tx_1 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_write_event_2 |
PDMA0_spi_main_0_tx_2 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_write_event_3 |
PDMA0_spi_main_0_tx_3 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_intr_spi_0 |
GICSS0_spi_204 |
GICSS0 |
MCSPI0 interrupt request |
level |
| MCSPI0 |
MCSPI0_intr_spi_0 |
ICSSM0_pr1_slv_intr_12 |
ICSSM0 |
MCSPI0 interrupt request |
level |
| MCSPI0 |
MCSPI0_intr_spi_0 |
WKUP_R5FSS0_CORE0_intr_204 |
WKUP_R5FSS0_CORE0 |
MCSPI0 interrupt request |
level |
| MCSPI1 |
MCSPI1_dma_read_event_0 |
PDMA0_spi_main_1_rx_0 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_read_event_1 |
PDMA0_spi_main_1_rx_1 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_read_event_2 |
PDMA0_spi_main_1_rx_2 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_read_event_3 |
PDMA0_spi_main_1_rx_3 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_write_event_0 |
PDMA0_spi_main_1_tx_0 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_write_event_1 |
PDMA0_spi_main_1_tx_1 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_write_event_2 |
PDMA0_spi_main_1_tx_2 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_write_event_3 |
PDMA0_spi_main_1_tx_3 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_intr_spi_0 |
GICSS0_spi_205 |
GICSS0 |
MCSPI1 interrupt request |
level |
| MCSPI1 |
MCSPI1_intr_spi_0 |
ICSSM0_pr1_slv_intr_15 |
ICSSM0 |
MCSPI1 interrupt request |
level |
| MCSPI1 |
MCSPI1_intr_spi_0 |
WKUP_R5FSS0_CORE0_intr_205 |
WKUP_R5FSS0_CORE0 |
MCSPI1 interrupt request |
level |
| MCSPI2 |
MCSPI2_dma_read_event_0 |
PDMA0_spi_main_2_rx_0 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_read_event_1 |
PDMA0_spi_main_2_rx_1 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_read_event_2 |
PDMA0_spi_main_2_rx_2 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_read_event_3 |
PDMA0_spi_main_2_rx_3 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_write_event_0 |
PDMA0_spi_main_2_tx_0 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_write_event_1 |
PDMA0_spi_main_2_tx_1 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_write_event_2 |
PDMA0_spi_main_2_tx_2 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_write_event_3 |
PDMA0_spi_main_2_tx_3 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_intr_spi_0 |
GICSS0_spi_206 |
GICSS0 |
MCSPI2 interrupt request |
level |
| MCSPI2 |
MCSPI2_intr_spi_0 |
WKUP_R5FSS0_CORE0_intr_206 |
WKUP_R5FSS0_CORE0 |
MCSPI2 interrupt request |
level |
| MCU_MCSPI0 |
MCU_MCSPI0_intr_spi_0 |
MCU_M4FSS0_CORE0_nvic_22 |
MCU_M4FSS0_CORE0 |
MCU_MCSPI0 interrupt request |
level |
| MCU_MCSPI0 |
MCU_MCSPI0_intr_spi_0 |
GICSS0_spi_208 |
GICSS0 |
MCU_MCSPI0 interrupt request |
level |
| MCU_MCSPI0 |
MCU_MCSPI0_intr_spi_0 |
WKUP_R5FSS0_CORE0_intr_207 |
WKUP_R5FSS0_CORE0 |
MCU_MCSPI0 interrupt request |
level |
| MCU_MCSPI1 |
MCU_MCSPI1_intr_spi_0 |
MCU_M4FSS0_CORE0_nvic_23 |
MCU_M4FSS0_CORE0 |
MCU_MCSPI1 interrupt request |
level |
| MCU_MCSPI1 |
MCU_MCSPI1_intr_spi_0 |
GICSS0_spi_209 |
GICSS0 |
MCU_MCSPI1 interrupt request |
level |
| MCU_MCSPI1 |
MCU_MCSPI1_intr_spi_0 |
WKUP_R5FSS0_CORE0_intr_208 |
WKUP_R5FSS0_CORE0 |
MCU_MCSPI1 interrupt request |
level |