SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| DDR16SS0 | 0F30 8110h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | ADDRESS_MIRRORING | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | REG_DIMM_ENABLE | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TRP_AB_F2_1 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TRP_AB_F1_1 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:26 | RESERVED | NONE | 0h | Reserved |
| 25:24 | ADDRESS_MIRRORING | R/W | 0h | Indicates which chip selects support address mirroring. Bit [0] controls cs0, bit [1] controls cs1, etc. Set each bit to 1 to enable. Reset Source: ctl_amod_g_rst_n |
| 23:17 | RESERVED | NONE | 0h | Reserved |
| 16 | REG_DIMM_ENABLE | R/W | 0h | Enable registered DIMM operation of the controller. Set to 1 to enable. Reset Source: ctl_amod_g_rst_n |
| 15:8 | TRP_AB_F2_1 | R/W | 0h | DRAM TRP all bank value in cycles. FC=2 Reset Source: ctl_amod_g_rst_n |
| 7:0 | TRP_AB_F1_1 | R/W | 0h | DRAM TRP all bank value in cycles. FC=1 Reset Source: ctl_amod_g_rst_n |