SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
The following are the PLLs in the device in MAIN domain:
Overview of the device PLLs with their reference clock options in MAIN domain is shown on Figure 6-41. For more specific information about PLLs see Section 6.4.5.5, PLLs Device-Specific Information.
The external muxes of choosing the reference clocks are glitch-free muxes.