SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
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| Instance Name | Physical Address |
|---|---|
| DDR16SS0 | 0F30 8640h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| TDFI_CTRLUPD_INTERVAL_F1 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TDFI_CTRLUPD_INTERVAL_F1 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TDFI_CTRLUPD_INTERVAL_F1 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TDFI_CTRLUPD_INTERVAL_F1 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | TDFI_CTRLUPD_INTERVAL_F1 | R/W | 0h | Defines the DFI tCTRLUPD_INTERVAL timing parameter [in DFI clocks], the maximum cycles between dfi_ctrlupd_req assertions. If programmed to a non-zero, a timing violation will cause an interrupt and bit [6] set in the UPDATE_ERROR_STATUS parameter. FC=1 Reset Source: ctl_amod_g_rst_n |