SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
The register configures the safety sub-region. Shadow register
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| Instance Name | Physical Address |
|---|---|
| DSS0 | 3020 62A0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | FRAMESKIP | THRESHOLD | |||||
| R | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| THRESHOLD | SEEDSELECT | CAPTUREMODE | ENABLE | ||||
| R/W | R/W | R/W | R/W | ||||
| 0h | 0h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:13 | RESERVED | R | 0h | |
| 12:11 | FRAMESKIP | R/W | 0h | Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped, 0x1: Even Frames are skipped starting from second frame after ENABLE, 0x2: Odd Frames are skipped starting from first frame after ENABLE, 0x3: Reserved 0 No frames are skipped
1 Even Frames are skipped starting from
second frame after ENABLE
2 Odd Frames are skipped starting from first
frame after ENABLE
3 Reserved |
| 10:3 | THRESHOLD | R/W | 0h | Allowed maximum number of frames with the same frame signature. When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1], a freeze frame detection will occur. Note: The freeze frame counter is cleared on reset -OR- MISR not enabled -OR- terminal count reached -OR- compare == no match |
| 2 | SEEDSELECT | R/W | 0h | Initial seed selection control 0 Initial seed is always 0xFFFF_FFFF
1 Initial seed is defined by
SAFETY_LFSR_START.SEED |
| 1 | CAPTUREMODE | R/W | 0h | Mode of operation of the safety check module 0 Frame freeze detect enabled 1 Data correctness check enabled |
| 0 | ENABLE | R/W | 0h | Safety check Enable for the region. Note: Transition from 0 to 1 clears the signature register |