SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
The bus interface clock VCLK is a fixed 250MHz. The bus interface clock may also be called ICLK in some documentation.
CORE_CLK is the clock that is used for the PRU cores. CORE_CLK can be selected from the module clock input CORE_CLK, or from VCLK_CLK. The user needs to configure the CORE_SYNC_REG[0] CORE_VBUSP_SYNC_EN bit to select which clock source is used.
The IEP counter clock IEP_CLK can be selected from the module clock input IEP_CLK, or from the PRUSS Core clock CORE_CLK. The user needs to configure the IEPCLK_REG[0] IEP_OCP_CLK_EN bit to select which clock source is used. In order to set IEP_CLK to VCLK_CLK, the user would set both CORE_SYNC_REG[0] CORE_VBUSP_SYNC_EN and IEPCLK_REG[0] IEP_OCP_CLK_EN bits to 1.