SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
The register defines the global alpha value for the video pipeline. Shadow register
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| Instance Name | Physical Address |
|---|---|
| DSS0 | 3020 61FCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GLOBALALPHA | |||||||
| R/W | |||||||
| FFh | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED | R | 0h | Reserved |
| 7:0 | GLOBALALPHA | R/W | FFh | Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 corresponds to fully opaque |