SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
| Step | Register/Bit Field/Programming Model | Value |
|---|---|---|
| Enable interrupt event | MAILBOX_IRQ_ENABLE_SET_j[0 + y*2] | 0x1 |
| User (processor) can perform another task until interrupt occurs See Section 8.1.1.3.1.3.2 for interrupt handling in receiving mode |