SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
The register configures the DMA buffer of the video pipeline. Shadow register
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| Instance Name | Physical Address |
|---|---|
| DSS0 | 3020 2218h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_212 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_212 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_212 | PRELOAD | ||||||
| R | R/W | ||||||
| 0h | 100h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PRELOAD | |||||||
| R/W | |||||||
| 100h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:12 | RESERVED_212 | R | 0h | Write 0's for future compatibility Reads return 0 |
| 11:0 | PRELOAD | R/W | 100h | DMA buffer preload value. Number of 128-bit words defining the preload value |