SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
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| Instance Name | Physical Address |
|---|---|
| DDR16SS0 | 0F30 A054h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PI_SWLVL_SM2_START | ||||||
| NONE | W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PI_SW_WDQLVL_RESP_1 | ||||||
| NONE | R | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_SWLVL_VREF_UPDATE_SLICE_1 | ||||||
| NONE | W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PI_SWLVL_RD_SLICE_1 | ||||||
| NONE | W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:25 | RESERVED | NONE | 0h | Reserved |
| 24 | PI_SWLVL_SM2_START | W | 0h | SW leveling start command for stage 2. WRITE-ONLY Reset Source: ctl_amod_g_rst_n |
| 23:18 | RESERVED | NONE | 0h | Reserved |
| 17:16 | PI_SW_WDQLVL_RESP_1 | R | 0h | Leveling response for data slice 1. READ-ONLY Reset Source: ctl_amod_g_rst_n |
| 15:9 | RESERVED | NONE | 0h | Reserved |
| 8 | PI_SWLVL_VREF_UPDATE_SLICE_1 | W | 0h | SW leveling vref update command in WDQ training. WRITE-ONLY Reset Source: ctl_amod_g_rst_n |
| 7:1 | RESERVED | NONE | 0h | Reserved |
| 0 | PI_SWLVL_RD_SLICE_1 | W | 0h | SW leveling read command in WDQ training. WRITE-ONLY Reset Source: ctl_amod_g_rst_n |