SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
| Instance | MAIN | MCU | WKUP |
|---|---|---|---|
| EQEP0 | ✓ | ||
| EQEP1 | ✓ | ||
| EQEP2 | ✓ |
| Module Instance | Power Sleep Controller | Power Domain | Module Domain | Index | Default | Controllable | Dependencies |
|---|---|---|---|---|---|---|---|
| EQEP0 | PSC0 | GP_Core_CTL | LPSC_main_IP | 34 | ON | YES | LPSC_DM2main_infra_ISO |
| EQEP1 | PSC0 | GP_Core_CTL | LPSC_main_IP | 34 | ON | YES | LPSC_DM2main_infra_ISO |
| EQEP2 | PSC0 | GP_Core_CTL | LPSC_main_IP | 34 | ON | YES | LPSC_DM2main_infra_ISO |
| Module Instance | Module Clock Input | Source Clock | Source Control Register | Description |
|---|---|---|---|---|
| EQEP0 | FICLK | MAIN_SYSCLK0/4 | functional and interface clock | |
| EQEP1 | FICLK | MAIN_SYSCLK0/4 | functional and interface clock | |
| EQEP2 | FICLK | MAIN_SYSCLK0/4 | functional and interface clock |
| Module Instance | Source | Description |
|---|---|---|
| EQEP0 | PSC0 | EQEP0 reset |
| EQEP1 | PSC0 | EQEP1 reset |
| EQEP2 | PSC0 | EQEP2 reset |
| Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
|---|---|---|---|---|---|
| EQEP0 | EQEP0_eqep_int_0 | GICSS0_spi_148 | GICSS0 | EQEP0 interrupt request | pulse |
| EQEP0 | EQEP0_eqep_int_0 | ICSSM0_pr1_slv_intr_13 | ICSSM0 | EQEP0 interrupt request | pulse |
| EQEP1 | EQEP1_eqep_int_0 | GICSS0_spi_149 | GICSS0 | EQEP1 interrupt request | pulse |
| EQEP1 | EQEP1_eqep_int_0 | ICSSM0_pr1_slv_intr_16 | ICSSM0 | EQEP1 interrupt request | pulse |
| EQEP2 | EQEP2_eqep_int_0 | GICSS0_spi_150 | GICSS0 | EQEP2 interrupt request | pulse |
| EQEP2 | EQEP2_eqep_int_0 | ICSSM0_pr1_slv_intr_17 | ICSSM0 | EQEP2 interrupt request | pulse |