| TIMER0 |
ICLK |
MAIN_SYSCLK0/4 |
|
interface clock |
| TIMER0 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=0 |
functional clock |
| TIMER0 |
FCLK |
HFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=0 |
functional clock |
| TIMER0 |
FCLK |
CLK_32K |
MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0 |
functional clock |
| TIMER0 |
FCLK |
MCU_HSDIV0_16FFT32 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1 |
functional clock |
| TIMER0 |
FCLK |
CLK_32K_RC |
MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2 |
functional clock |
| TIMER0 |
FCLK |
LFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3 |
functional clock |
| TIMER0 |
FCLK |
CPSW0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=10 |
functional clock |
| TIMER0 |
FCLK |
CPSW0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=11 |
functional clock |
| TIMER0 |
FCLK |
MAIN_PLL0_HSDIV7_CLKOUT |
MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=2 |
functional clock |
| TIMER0 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=3 |
functional clock |
| TIMER0 |
FCLK |
MCU_EXT_REFCLK0 |
MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=4 |
functional clock |
| TIMER0 |
FCLK |
EXT_REFCLK1 |
MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=5 |
functional clock |
| TIMER0 |
FCLK |
CP_GEMAC_CPTS_REF_CLK |
MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=7 |
functional clock |
| TIMER0 |
FCLK |
MAIN_PLL1_HSDIV3_CLKOUT |
MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=8 |
functional clock |
| TIMER0 |
FCLK |
MAIN_PLL2_HSDIV6_CLKOUT |
MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=9 |
functional clock |
| TIMER1 |
ICLK |
MAIN_SYSCLK0/4 |
|
interface clock |
| TIMER1 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=0 |
functional clock |
| TIMER1 |
FCLK |
HFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=0 |
functional clock |
| TIMER1 |
FCLK |
CLK_32K |
MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0 |
functional clock |
| TIMER1 |
FCLK |
MCU_HSDIV0_16FFT32 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1 |
functional clock |
| TIMER1 |
FCLK |
CLK_32K_RC |
MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2 |
functional clock |
| TIMER1 |
FCLK |
LFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3 |
functional clock |
| TIMER1 |
FCLK |
CPSW0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=10 |
functional clock |
| TIMER1 |
FCLK |
CPSW0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=11 |
functional clock |
| TIMER1 |
FCLK |
MAIN_PLL0_HSDIV7_CLKOUT |
MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=2 |
functional clock |
| TIMER1 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=3 |
functional clock |
| TIMER1 |
FCLK |
MCU_EXT_REFCLK0 |
MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=4 |
functional clock |
| TIMER1 |
FCLK |
EXT_REFCLK1 |
MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=5 |
functional clock |
| TIMER1 |
FCLK |
CP_GEMAC_CPTS_REF_CLK |
MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=7 |
functional clock |
| TIMER1 |
FCLK |
MAIN_PLL1_HSDIV3_CLKOUT |
MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=8 |
functional clock |
| TIMER1 |
FCLK |
MAIN_PLL2_HSDIV6_CLKOUT |
MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=9 |
functional clock |
| TIMER2 |
ICLK |
MAIN_SYSCLK0/4 |
|
interface clock |
| TIMER2 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=0 |
functional clock |
| TIMER2 |
FCLK |
HFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=0 |
functional clock |
| TIMER2 |
FCLK |
CLK_32K |
MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0 |
functional clock |
| TIMER2 |
FCLK |
MCU_HSDIV0_16FFT32 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1 |
functional clock |
| TIMER2 |
FCLK |
CLK_32K_RC |
MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2 |
functional clock |
| TIMER2 |
FCLK |
LFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3 |
functional clock |
| TIMER2 |
FCLK |
CPSW0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=10 |
functional clock |
| TIMER2 |
FCLK |
CPSW0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=11 |
functional clock |
| TIMER2 |
FCLK |
MAIN_PLL0_HSDIV7_CLKOUT |
MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=2 |
functional clock |
| TIMER2 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=3 |
functional clock |
| TIMER2 |
FCLK |
MCU_EXT_REFCLK0 |
MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=4 |
functional clock |
| TIMER2 |
FCLK |
EXT_REFCLK1 |
MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=5 |
functional clock |
| TIMER2 |
FCLK |
CP_GEMAC_CPTS_REF_CLK |
MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=7 |
functional clock |
| TIMER2 |
FCLK |
MAIN_PLL1_HSDIV3_CLKOUT |
MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=8 |
functional clock |
| TIMER2 |
FCLK |
MAIN_PLL2_HSDIV6_CLKOUT |
MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=9 |
functional clock |
| TIMER3 |
ICLK |
MAIN_SYSCLK0/4 |
|
interface clock |
| TIMER3 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=0 |
functional clock |
| TIMER3 |
FCLK |
HFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=0 |
functional clock |
| TIMER3 |
FCLK |
CLK_32K |
MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0 |
functional clock |
| TIMER3 |
FCLK |
MCU_HSDIV0_16FFT32 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1 |
functional clock |
| TIMER3 |
FCLK |
CLK_32K_RC |
MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2 |
functional clock |
| TIMER3 |
FCLK |
LFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3 |
functional clock |
| TIMER3 |
FCLK |
CPSW0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=10 |
functional clock |
| TIMER3 |
FCLK |
CPSW0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=11 |
functional clock |
| TIMER3 |
FCLK |
MAIN_PLL0_HSDIV7_CLKOUT |
MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=2 |
functional clock |
| TIMER3 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=3 |
functional clock |
| TIMER3 |
FCLK |
MCU_EXT_REFCLK0 |
MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=4 |
functional clock |
| TIMER3 |
FCLK |
EXT_REFCLK1 |
MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=5 |
functional clock |
| TIMER3 |
FCLK |
CP_GEMAC_CPTS_REF_CLK |
MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=7 |
functional clock |
| TIMER3 |
FCLK |
MAIN_PLL1_HSDIV3_CLKOUT |
MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=8 |
functional clock |
| TIMER3 |
FCLK |
MAIN_PLL2_HSDIV6_CLKOUT |
MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=9 |
functional clock |
| TIMER4 |
ICLK |
MAIN_SYSCLK0/4 |
|
interface clock |
| TIMER4 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=0 |
functional clock |
| TIMER4 |
FCLK |
HFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=0 |
functional clock |
| TIMER4 |
FCLK |
CLK_32K |
MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0 |
functional clock |
| TIMER4 |
FCLK |
MCU_HSDIV0_16FFT32 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1 |
functional clock |
| TIMER4 |
FCLK |
CLK_32K_RC |
MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2 |
functional clock |
| TIMER4 |
FCLK |
LFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3 |
functional clock |
| TIMER4 |
FCLK |
CPSW0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=10 |
functional clock |
| TIMER4 |
FCLK |
CPSW0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=11 |
functional clock |
| TIMER4 |
FCLK |
MAIN_PLL0_HSDIV7_CLKOUT |
MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=2 |
functional clock |
| TIMER4 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=3 |
functional clock |
| TIMER4 |
FCLK |
MCU_EXT_REFCLK0 |
MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=4 |
functional clock |
| TIMER4 |
FCLK |
EXT_REFCLK1 |
MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=5 |
functional clock |
| TIMER4 |
FCLK |
CP_GEMAC_CPTS_REF_CLK |
MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=7 |
functional clock |
| TIMER4 |
FCLK |
MAIN_PLL1_HSDIV3_CLKOUT |
MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=8 |
functional clock |
| TIMER4 |
FCLK |
MAIN_PLL2_HSDIV6_CLKOUT |
MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=9 |
functional clock |
| TIMER5 |
ICLK |
MAIN_SYSCLK0/4 |
|
interface clock |
| TIMER5 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=0 |
functional clock |
| TIMER5 |
FCLK |
HFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=0 |
functional clock |
| TIMER5 |
FCLK |
CLK_32K |
MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0 |
functional clock |
| TIMER5 |
FCLK |
MCU_HSDIV0_16FFT32 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1 |
functional clock |
| TIMER5 |
FCLK |
CLK_32K_RC |
MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2 |
functional clock |
| TIMER5 |
FCLK |
LFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3 |
functional clock |
| TIMER5 |
FCLK |
CPSW0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=10 |
functional clock |
| TIMER5 |
FCLK |
CPSW0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=11 |
functional clock |
| TIMER5 |
FCLK |
MAIN_PLL0_HSDIV7_CLKOUT |
MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=2 |
functional clock |
| TIMER5 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=3 |
functional clock |
| TIMER5 |
FCLK |
MCU_EXT_REFCLK0 |
MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=4 |
functional clock |
| TIMER5 |
FCLK |
EXT_REFCLK1 |
MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=5 |
functional clock |
| TIMER5 |
FCLK |
CP_GEMAC_CPTS_REF_CLK |
MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=7 |
functional clock |
| TIMER5 |
FCLK |
MAIN_PLL1_HSDIV3_CLKOUT |
MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=8 |
functional clock |
| TIMER5 |
FCLK |
MAIN_PLL2_HSDIV6_CLKOUT |
MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=9 |
functional clock |
| TIMER6 |
ICLK |
MAIN_SYSCLK0/4 |
|
interface clock |
| TIMER6 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=0 |
functional clock |
| TIMER6 |
FCLK |
HFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=0 |
functional clock |
| TIMER6 |
FCLK |
CLK_32K |
MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0 |
functional clock |
| TIMER6 |
FCLK |
MCU_HSDIV0_16FFT32 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1 |
functional clock |
| TIMER6 |
FCLK |
CLK_32K_RC |
MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2 |
functional clock |
| TIMER6 |
FCLK |
LFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3 |
functional clock |
| TIMER6 |
FCLK |
CPSW0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=10 |
functional clock |
| TIMER6 |
FCLK |
CPSW0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=11 |
functional clock |
| TIMER6 |
FCLK |
MAIN_PLL0_HSDIV7_CLKOUT |
MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=2 |
functional clock |
| TIMER6 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=3 |
functional clock |
| TIMER6 |
FCLK |
MCU_EXT_REFCLK0 |
MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=4 |
functional clock |
| TIMER6 |
FCLK |
EXT_REFCLK1 |
MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=5 |
functional clock |
| TIMER6 |
FCLK |
CP_GEMAC_CPTS_REF_CLK |
MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=7 |
functional clock |
| TIMER6 |
FCLK |
MAIN_PLL1_HSDIV3_CLKOUT |
MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=8 |
functional clock |
| TIMER6 |
FCLK |
MAIN_PLL2_HSDIV6_CLKOUT |
MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=9 |
functional clock |
| TIMER7 |
ICLK |
MAIN_SYSCLK0/4 |
|
interface clock |
| TIMER7 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=0 |
functional clock |
| TIMER7 |
FCLK |
HFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=0 |
functional clock |
| TIMER7 |
FCLK |
CLK_32K |
MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0 |
functional clock |
| TIMER7 |
FCLK |
MCU_HSDIV0_16FFT32 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1 |
functional clock |
| TIMER7 |
FCLK |
CLK_32K_RC |
MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2 |
functional clock |
| TIMER7 |
FCLK |
LFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3 |
functional clock |
| TIMER7 |
FCLK |
CPSW0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=10 |
functional clock |
| TIMER7 |
FCLK |
CPSW0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=11 |
functional clock |
| TIMER7 |
FCLK |
MAIN_PLL0_HSDIV7_CLKOUT |
MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=2 |
functional clock |
| TIMER7 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=3 |
functional clock |
| TIMER7 |
FCLK |
MCU_EXT_REFCLK0 |
MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=4 |
functional clock |
| TIMER7 |
FCLK |
EXT_REFCLK1 |
MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=5 |
functional clock |
| TIMER7 |
FCLK |
CP_GEMAC_CPTS_REF_CLK |
MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=7 |
functional clock |
| TIMER7 |
FCLK |
MAIN_PLL1_HSDIV3_CLKOUT |
MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=8 |
functional clock |
| TIMER7 |
FCLK |
MAIN_PLL2_HSDIV6_CLKOUT |
MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=9 |
functional clock |
| MCU_TIMER0 |
ICLK |
MCU_SYSCLK0/4 |
|
interface clock |
| MCU_TIMER0 |
FCLK |
CLK_12M_RC |
MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=0 |
functional clock |
| MCU_TIMER0 |
FCLK |
HFOSC0 (INSTANCE) |
MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=0 |
functional clock |
| MCU_TIMER0 |
FCLK |
MCU_SYSCLK0 |
MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=1 |
functional clock |
| MCU_TIMER0 |
FCLK |
CLK_12M_RC |
MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=2 |
functional clock |
| MCU_TIMER0 |
FCLK |
MCU_PLL0_HSDIV3_CLKOUT |
MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=3 |
functional clock |
| MCU_TIMER0 |
FCLK |
MCU_EXT_REFCLK0 |
MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=4 |
functional clock |
| MCU_TIMER0 |
FCLK |
CLK_32K |
MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=5
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0 |
functional clock |
| MCU_TIMER0 |
FCLK |
MCU_HSDIV0_16FFT32 (INSTANCE) |
MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=5
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1 |
functional clock |
| MCU_TIMER0 |
FCLK |
CLK_32K_RC |
MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=5
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2 |
functional clock |
| MCU_TIMER0 |
FCLK |
LFOSC0 (INSTANCE) |
MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=5
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3 |
functional clock |
| MCU_TIMER0 |
FCLK |
CPSW0 (INSTANCE) |
MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=6 |
functional clock |
| MCU_TIMER0 |
FCLK |
CLK_32K_RC |
MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=7 |
functional clock |
| MCU_TIMER1 |
ICLK |
MCU_SYSCLK0/4 |
|
interface clock |
| MCU_TIMER1 |
FCLK |
CLK_12M_RC |
MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=0 |
functional clock |
| MCU_TIMER1 |
FCLK |
HFOSC0 (INSTANCE) |
MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=0 |
functional clock |
| MCU_TIMER1 |
FCLK |
MCU_SYSCLK0 |
MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=1 |
functional clock |
| MCU_TIMER1 |
FCLK |
CLK_12M_RC |
MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=2 |
functional clock |
| MCU_TIMER1 |
FCLK |
MCU_PLL0_HSDIV3_CLKOUT |
MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=3 |
functional clock |
| MCU_TIMER1 |
FCLK |
MCU_EXT_REFCLK0 |
MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=4 |
functional clock |
| MCU_TIMER1 |
FCLK |
CLK_32K |
MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=5
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0 |
functional clock |
| MCU_TIMER1 |
FCLK |
MCU_HSDIV0_16FFT32 (INSTANCE) |
MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=5
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1 |
functional clock |
| MCU_TIMER1 |
FCLK |
CLK_32K_RC |
MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=5
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2 |
functional clock |
| MCU_TIMER1 |
FCLK |
LFOSC0 (INSTANCE) |
MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=5
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3 |
functional clock |
| MCU_TIMER1 |
FCLK |
CPSW0 (INSTANCE) |
MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=6 |
functional clock |
| MCU_TIMER1 |
FCLK |
CLK_32K_RC |
MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=7 |
functional clock |
| MCU_TIMER2 |
ICLK |
MCU_SYSCLK0/4 |
|
interface clock |
| MCU_TIMER2 |
FCLK |
CLK_12M_RC |
MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=0 |
functional clock |
| MCU_TIMER2 |
FCLK |
HFOSC0 (INSTANCE) |
MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=0 |
functional clock |
| MCU_TIMER2 |
FCLK |
MCU_SYSCLK0 |
MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=1 |
functional clock |
| MCU_TIMER2 |
FCLK |
CLK_12M_RC |
MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=2 |
functional clock |
| MCU_TIMER2 |
FCLK |
MCU_PLL0_HSDIV3_CLKOUT |
MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=3 |
functional clock |
| MCU_TIMER2 |
FCLK |
MCU_EXT_REFCLK0 |
MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=4 |
functional clock |
| MCU_TIMER2 |
FCLK |
CLK_32K |
MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=5
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0 |
functional clock |
| MCU_TIMER2 |
FCLK |
MCU_HSDIV0_16FFT32 (INSTANCE) |
MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=5
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1 |
functional clock |
| MCU_TIMER2 |
FCLK |
CLK_32K_RC |
MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=5
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2 |
functional clock |
| MCU_TIMER2 |
FCLK |
LFOSC0 (INSTANCE) |
MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=5
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3 |
functional clock |
| MCU_TIMER2 |
FCLK |
CPSW0 (INSTANCE) |
MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=6 |
functional clock |
| MCU_TIMER2 |
FCLK |
CLK_32K_RC |
MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=7 |
functional clock |
| MCU_TIMER3 |
ICLK |
MCU_SYSCLK0/4 |
|
interface clock |
| MCU_TIMER3 |
FCLK |
CLK_12M_RC |
MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=0 |
functional clock |
| MCU_TIMER3 |
FCLK |
HFOSC0 (INSTANCE) |
MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=0 |
functional clock |
| MCU_TIMER3 |
FCLK |
MCU_SYSCLK0 |
MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=1 |
functional clock |
| MCU_TIMER3 |
FCLK |
CLK_12M_RC |
MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=2 |
functional clock |
| MCU_TIMER3 |
FCLK |
MCU_PLL0_HSDIV3_CLKOUT |
MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=3 |
functional clock |
| MCU_TIMER3 |
FCLK |
MCU_EXT_REFCLK0 |
MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=4 |
functional clock |
| MCU_TIMER3 |
FCLK |
CLK_32K |
MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=5
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0 |
functional clock |
| MCU_TIMER3 |
FCLK |
MCU_HSDIV0_16FFT32 (INSTANCE) |
MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=5
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1 |
functional clock |
| MCU_TIMER3 |
FCLK |
CLK_32K_RC |
MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=5
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2 |
functional clock |
| MCU_TIMER3 |
FCLK |
LFOSC0 (INSTANCE) |
MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=5
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3 |
functional clock |
| MCU_TIMER3 |
FCLK |
CPSW0 (INSTANCE) |
MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=6 |
functional clock |
| MCU_TIMER3 |
FCLK |
CLK_32K_RC |
MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=7 |
functional clock |
| WKUP_TIMER0 |
ICLK |
DM_CLK/2 |
|
interface clock |
| WKUP_TIMER0 |
FCLK |
CLK_12M_RC |
WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=0 |
functional clock |
| WKUP_TIMER0 |
FCLK |
HFOSC0 (INSTANCE) |
WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=0 |
functional clock |
| WKUP_TIMER0 |
FCLK |
DM_CLK |
WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=1 |
functional clock |
| WKUP_TIMER0 |
FCLK |
CLK_12M_RC |
WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=2 |
functional clock |
| WKUP_TIMER0 |
FCLK |
MCU_PLL0_HSDIV3_CLKOUT |
WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=3 |
functional clock |
| WKUP_TIMER0 |
FCLK |
MCU_EXT_REFCLK0 |
WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=4 |
functional clock |
| WKUP_TIMER0 |
FCLK |
CLK_32K |
WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=5
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0 |
functional clock |
| WKUP_TIMER0 |
FCLK |
MCU_HSDIV0_16FFT32 (INSTANCE) |
WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=5
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1 |
functional clock |
| WKUP_TIMER0 |
FCLK |
CLK_32K_RC |
WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=5
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2 |
functional clock |
| WKUP_TIMER0 |
FCLK |
LFOSC0 (INSTANCE) |
WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=5
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3 |
functional clock |
| WKUP_TIMER0 |
FCLK |
CPSW0 (INSTANCE) |
WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=6 |
functional clock |
| WKUP_TIMER0 |
FCLK |
CLK_32K_RC |
WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=7 |
functional clock |
| WKUP_TIMER1 |
ICLK |
DM_CLK/2 |
|
interface clock |
| WKUP_TIMER1 |
FCLK |
CLK_12M_RC |
WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=0 |
functional clock |
| WKUP_TIMER1 |
FCLK |
HFOSC0 (INSTANCE) |
WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=0 |
functional clock |
| WKUP_TIMER1 |
FCLK |
DM_CLK |
WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=1 |
functional clock |
| WKUP_TIMER1 |
FCLK |
CLK_12M_RC |
WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=2 |
functional clock |
| WKUP_TIMER1 |
FCLK |
MCU_PLL0_HSDIV3_CLKOUT |
WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=3 |
functional clock |
| WKUP_TIMER1 |
FCLK |
MCU_EXT_REFCLK0 |
WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=4 |
functional clock |
| WKUP_TIMER1 |
FCLK |
CLK_32K |
WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=5
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0 |
functional clock |
| WKUP_TIMER1 |
FCLK |
MCU_HSDIV0_16FFT32 (INSTANCE) |
WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=5
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1 |
functional clock |
| WKUP_TIMER1 |
FCLK |
CLK_32K_RC |
WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=5
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2 |
functional clock |
| WKUP_TIMER1 |
FCLK |
LFOSC0 (INSTANCE) |
WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=5
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3 |
functional clock |
| WKUP_TIMER1 |
FCLK |
CPSW0 (INSTANCE) |
WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=6 |
functional clock |
| WKUP_TIMER1 |
FCLK |
CLK_32K_RC |
WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=7 |
functional clock |