SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
The goal of the basic high-level programming model is to introduce a top-down approach to users that need to configure the GPMC module.
Figure 12-211 and Table 12-216 through Table 12-217 show a programming model top-level diagram for the GPMC, and a description of each step. Each block of the diagram is described in one of the following sections through a set of registers to configure.
Figure 12-211 Programming Model Top-Level Diagram| Step | Description |
|---|---|
| NOR Memory Type | See Table 12-218. |
| NOR Chip-Select Configuration | See Table 12-219. |
| NOR Timings Configuration | See Table 12-220. |
| WAIT Pin Configuration | See Table 12-228. |
| Enable Chip-Select | See Table 12-229. |
| Step | Description |
|---|---|
| NAND Memory Type | See Table 12-223. |
| NAND Chip-Select Configuration | See Table 12-224. |
| Write Operations (Asynchronous) | See Table 12-225. |
| Read Operations (Asynchronous) | See Table 12-225. |
| ECC Engine | See Table 12-226. |
| Prefetch and Write-Posting Engine | See Table 12-227. |
| WAIT Pin Configuration | See Table 12-228. |
| Enable Chip-Select | See Table 12-229. |