SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
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| Instance Name | Physical Address |
|---|---|
| DDR16SS0 | 0F30 8578h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| INT_ACK_INIT | |||||||
| W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| INT_ACK_FREQ | |||||||
| W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| MC_RESERVED20 | |||||||
| W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INT_ACK_DFI | |||||||
| W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:24 | INT_ACK_INIT | W | 0h | Clear status of the INT_STATUS_INIT parameter. WRITE-ONLY Reset Source: ctl_amod_g_rst_n |
| 23:16 | INT_ACK_FREQ | W | 0h | Clear status of the INT_STATUS_FREQ parameter. WRITE-ONLY Reset Source: ctl_amod_g_rst_n |
| 15:8 | MC_RESERVED20 | W | 0h | Reserved |
| 7:0 | INT_ACK_DFI | W | 0h | Clear status of the INT_STATUS_DFI parameter. WRITE-ONLY Reset Source: ctl_amod_g_rst_n |