SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
MCU domain has a M4F micro-controller core, which is natively 32b processor. A dedicated RAT module is added to allow M4F processor to access full 36b common SoC address map.
| CortexM4 Start Address (32 bit) | CortexM4 End Address (32 bit) | Which end points MCU M4F will access | Additional Description |
|---|---|---|---|
| 0x0000_0000 | 0x0002_FFFF | MCU M4F's I-RAM | Other initiator access MCU M4F's I-RAM using address 0x0500_0000 |
| 0x0003_0000 | 0x0003_FFFF | MCU M4F's D-RaM | Other initiator access MCU M4F's I-RAM using address 0x0504_0000 |
| 0x0004_0000 | 0x0083_FFFF | Any transactions hitting this address range coming from MCU M4F will go through RAT for address re-mapping before reaching other end points. | Can be mapped to any memory regions in the SoC common memory map except MCU M4F's I/D RAM. |
| 0x0084_0000 | 0x441F_FFFF | Reserved region. Any transaction coming from M4F hitting this region will be gracefully terminated | |
| 0x4420_0000 | 0x4420_0FFF | MCU M4F core's RAT config | Other initiators access this end point using the SoC common memory map place MCU M4F's RAT config at 0x05FF_0000 |
| 0x4420_1000 | 0x4420_13FF | MCU M4F core's ECC Aggregator | Other initiators access this end point using the SoC common memory map place MCU M4F's ECC aggregator at 0x05FF_1000 |
| 0x4420_1400 | 0x5FFF_FFFF | Reserved region. Any transaction coming from M4F hitting this region will be gracefully terminated | |
| 0x6000_0000 | 0xDFFF_FFFF | Any transactions hitting this address range coming from MCU M4F will go through RAT for address re-mapping before reaching other end points. | Can be mapped to any memory regions in the SoC common memory map except MCU M4F's I/D RAM. |
| 0xE000_0000 | 0xE000_0FFF | MCU M4F core's ITM | Only visiable by MCU M4F core itself. |
| 0xE000_1000 | 0xE000_1FFF | MCU M4F core's DWT | |
| 0xE000_2000 | 0xE000_2FFF | MCU M4F core's FBP | |
| 0xE000_E000 | 0xE000_EFFF | MCU M4F core's SCS | |
| 0xE004_2000 | 0xE004_2FFF | MCU M4F core's CTI | |
| 0xE000_E000 | 0xE000_E4EF | MCU M4F core's NVIC config region | |
| 0xE00F_F000 | MCU M4F core's ROM Table | ||
| 0xE010_0000 | 0xFFFF_FFFF | Any transactions hitting this address range coming from MCU M4F will go through RAT for address re-mapping before reaching other end points. |