SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
| Instance | MAIN | MCU | WKUP |
|---|---|---|---|
| csi_rx_if0 | ✓ |
| Module Instance | Power Sleep Controller | Power Domain | Module Domain | Index | Default | Controllable | Dependencies |
|---|---|---|---|---|---|---|---|
| csi_rx_if0 | PSC0 | GP_Core_CTL | LPSC_CSI_RX_0 | 25 | OFF | YES | LPSC_DPHY_0 |
| Module Instance | Module Clock Input | Source Clock | Source Control Register | Description |
|---|---|---|---|---|
| csi_rx_if0 | CSI_RX_MAIN_CLK | MAIN_SYSCLK0 | main_clk clock runs the csi2 core and psil dma. | |
| csi_rx_if0 | CSI_RX_BYTE_CLK | DPHY_RX0 (INSTANCE) | byte_clk is the clock supplied by the dphy_rx pll and is divided down to byte clock. the dphy_rx is designed for max of 10gbps. this translates to a max byte clock of 312.5mhz. the clock is inactive when dphy_rx is not in hs operation | |
| csi_rx_if0 | CSI_RX_VBUS_CLK | MAIN_SYSCLK0/2 | interface configuration clock that runs at half the speed of the main_clk | |
| csi_rx_if0 | CSI_RX_VP_CLK | MAIN_SYSCLK0 | video port clock |
| Module Instance | Source | Description |
|---|---|---|
| csi_rx_if0 | PSC0 | csi_rx_if0 reset |
| Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
|---|---|---|---|---|---|
| csi_rx_if0 | csi_rx_if0_corr_level_0 | ESM0_esm_lvl_event_66 | ESM0 | csi_rx_if0 interrupt request | level |
| csi_rx_if0 | csi_rx_if0_csi_err_irq_0 | ESM0_esm_lvl_event_0 | ESM0 | csi_rx_if0 interrupt request | level |
| csi_rx_if0 | csi_rx_if0_csi_err_irq_0 | GICSS0_spi_175 | GICSS0 | csi_rx_if0 interrupt request | level |
| csi_rx_if0 | csi_rx_if0_csi_fatal_0 | ESM0_esm_lvl_event_70 | ESM0 | csi_rx_if0 interrupt request | level |
| csi_rx_if0 | csi_rx_if0_csi_irq_0 | GICSS0_spi_173 | GICSS0 | csi_rx_if0 interrupt request | level |
| csi_rx_if0 | csi_rx_if0_csi_level_0 | ESM0_esm_lvl_event_72 | ESM0 | csi_rx_if0 interrupt request | level |
| csi_rx_if0 | csi_rx_if0_csi_level_0 | GICSS0_spi_174 | GICSS0 | csi_rx_if0 interrupt request | level |
| csi_rx_if0 | csi_rx_if0_csi_nonfatal_0 | ESM0_esm_lvl_event_71 | ESM0 | csi_rx_if0 interrupt request | level |
| csi_rx_if0 | csi_rx_if0_uncorr_level_0 | ESM0_esm_lvl_event_77 | ESM0 | csi_rx_if0 interrupt request | level |