SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
ID Register 3
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| Instance Name | Physical Address |
|---|---|
| A53SS0 | 0007 3033 01ECh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| NOOVERFLOW | NUMPROC | SYSSTALL | STALLCTL | SYNCPR | TRCERR | ||
| R/W | R/W | R/W | R/W | R/W | R/W | ||
| 0h | 0h | 1h | 1h | 0h | 1h | ||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| EXLEVEL_NS | EXLEVEL_S | ||||||
| R/W | R/W | ||||||
| 7h | Bh | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RES0_TRCIDR3_15_12 | CCITMIN | ||||||
| R/W | R/W | ||||||
| 0h | 4h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CCITMIN | |||||||
| R/W | |||||||
| 4h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | NOOVERFLOW | R/W | 0h | Indicates if TRCSTALLCTLR.NOOVERFLOW is supported: 0 TRCSTALLCTLR.NOOVERFLOW is not supported, or STALLCTL==0. 1 TRCSTALLCTLR.NOOVERFLOW is supported. |
| 30:28 | NUMPROC | R/W | 0h | Indicates the number of processors available for tracing. The possible values are: 000 The trace unit can trace one processor. 001 The trace unit can trace two processors. 010 The trace unit can trace three processors. and so on up to 0b111, which indicates the trace unit can trace eight processors.This field sets the maximum value of TRCPROCSELR.PROCSEL. |
| 27 | SYSSTALL | R/W | 1h | Indicates if the implementation can support stall control: 0 The system does not support stall control of the processor. 1 The system can support stall control of the processor. The system supports stalling of the processor only when SYSSTALL==1 and STALLCTL==1. |
| 26 | STALLCTL | R/W | 1h | Indicates if TRCSTALLCTLR is supported: 0 TRCSTALLCTLR is not supported. 1 TRCSTALLCTLR is supported. |
| 25 | SYNCPR | R/W | 0h | Indicates if an implementation has a fixed synchronization period: 0 TRCSYNCPR is read-write so software can change the synchronization period. 1 TRCSYNCPR is read-only so the synchronization period is fixed. |
| 24 | TRCERR | R/W | 1h | Indicates if TRCVICTLR.TRCERR is supported: 0 TRCVICTLR.TRCERR is not supported 1 TRCVICTLR.TRCERR is supported. |
| 23:20 | EXLEVEL_NS | R/W | 7h | In Non-secure state, each bit indicates whether instruction tracing is supported for the corresponding exception level: 0 In Non-secure state, exception level n is not supported so the corresponding bits in TRCACATRn.EXLEVEL_NS and TRCVICTLR.EXLEVEL_NS are not supported. 1 In Non-secure state, exception level n is supported so the corresponding bits in TRCACATRn.EXLEVEL_NS and TRCVICTLR.EXLEVEL_NS are supported. The exception levels are:Bit[20]Exception level 0.Bit[21]Exception level 1.Bit[22]Exception level 2.Bit[23]SBZ. EXLEVEL_NS[3] is never implemented. |
| 19:16 | EXLEVEL_S | R/W | Bh | In Secure state, each bit indicates whether instruction tracing is supported for the corresponding exception level: 0 In Secure state, exception level n is not supported so the corresponding bits in TRCACATRn.EXLEVEL_S and TRCVICTLR.EXLEVEL_S are not supported. 1 In Secure state, exception level n is supported so the corresponding bits in TRCACATRn.EXLEVEL_S and TRCVICTLR.EXLEVEL_S are supported. The exception levels are:Bit[16]Exception level 0.Bit[17]Exception level 1.Bit[18]SBZ. EXLEVEL_S[2] is never implemented.Bit[19]Exception level 3. |
| 15:12 | RES0_TRCIDR3_15_12 | R/W | 0h | Reserved, RES0. |
| 11:0 | CCITMIN | R/W | 4h | Indicates the minimum value that can be programmed in TRCCCCTLR.THRESHOLD.When cycle counting in the instruction trace is supported, that is TRCIDR0.TRCCCI==1, then the minimum value of this field is 0x001, otherwise it is 0x000. |