SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
The industrial digital I/Os supported by the PRUSS IEP peripheral are described in theTable 7-74:
| Direction | Port | Mapped to Device I/Os | Notes |
|---|---|---|---|
| output | PRG<k>_IEP0_EDIO_DATA_IN_OUT[0:31] | PRG0_IEP0_EDIO_DATA_IN_OUT[31:28] PRG1_IEP0_EDIO_DATA_IN_OUT[31:28] | Only PRG<k>_IEP0_EDIO_DATA_IN_OUT[31:28] are exported to device pins as a bidirectional. |
| output | PRG<k>_EDIO_DATA_OUT_EN[0:31] | No | Optional tri-state control for DATA_OUT |
| output | PRG<k>_IEP0_EDIO_OUTVALID | PRG0_IEP0_EDIO_OUTVALID PRG1_IEP0_EDIO_OUTVALID | Will pulse even same data |
| output | PRG<k>_EDIO_SOF | No | PRU<0/1>_RX_SOF defined by IEP_DIGIO_EXP_REG[12] SOF_SEL |
| input | PRG<k>_EDIO_OE_EXT | No | |
| output | PRG<k>_EDIO_WD_TRIG | No | Just export of IEP_WD_STATUS_REG[0] PD_WD_STAT |
| output | PRG<k>_EDIO_DATA_ENA | No | Reserved. Driven low. |
| input | PRG<k>_IEP<n>_EDC_LATCH_IN0 | PRG0_IEP<n>_EDC_LATCH_IN0 PRG1_IEP<n>_EDC_LATCH_IN0 | |
| input | PRG<k>_IEP<n>_EDC_LATCH_IN1 | PRG0_IEP<n>_EDC_LATCH_IN1 PRG1_IEP<n>_EDC_LATCH_IN1 | |
| output | PRG<k>_IEP<n>_EDC_SYNC_OUT0 | PRG0_IEP<n>_EDC_SYNC_OUT0 PRG1_IEP<n>_EDC_SYNC_OUT0 | |
| output | PRG<k>_IEP<n>_EDC_SYNC_OUT1 | PRG0_IEP<n>_EDC_SYNC_OUT1 PRG1_IEP<n>_EDC_SYNC_OUT1 |