SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
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| Instance Name | Physical Address |
|---|---|
| CTRL_MMR0 | 0010 A000h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | OBSCLK0_CTRL_CLK_DIV_LD_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| OBSCLK0_CTRL_CLK_DIV_PROXY | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | OBSCLK0_CTRL_CLK_SEL_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | 7h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:17 | RESERVED | NONE | 0h | Reserved |
| 16 | OBSCLK0_CTRL_CLK_DIV_LD_PROXY | R/W | 0h | Load the output divider value Writing 1 to this bit will generate a load pulse to load the OBSCLK0 divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed. Reset Source: mod_por_rst_n |
| 15:8 | OBSCLK0_CTRL_CLK_DIV_PROXY | R/W | 0h | OBSCLK0 output divider Divides the selected clock by clkdiv+1 for output to the OBSCLK0 pins. Supports divide by 1 to 256 (default to 1). To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Reset Source: mod_por_rst_n |
| 7:5 | RESERVED | NONE | 0h | Reserved |
| 4:0 | OBSCLK0_CTRL_CLK_SEL_PROXY | R/W | 7h | OBSCLK0 clock source selection. Selects the source of the clock to be divided by the OBSCLK0 divider and output on the OBSCLK0 pin. Field values (others are reserved): 5'b00000 - MAIN_PLL0_HSDIV0_CLKOUT 5'b00001 - MAIN_PLL1_HSDIV0_CLKOUT 5'b00010 - MAIN_PLL2_HSDIV0_CLKOUT 5'b00011 - MAIN_PLL8_HSDIV0_CLKOUT 5'b00100 - MAIN_PLL12_HSDIV0_CLKOUT 5'b00101 - CLK_12M_RC 5'b00110 - HFOSC0_CLKOUT_32K 5'b00111 - PLLCTRL_OBSCLK 5'b01000 - HFOSC0_CLKOUT 5'b01001 - CLK_32K 5'b01010 - cpsw2g_cpts_genf0 5'b01011 - cpsw2g_cpts_genf1 5'b01100 - MCU_PLL0_HSDIV0_CLKOUT 5'b01101 - MAIN_PLL15_HSDIV0_CLKOUT 5'b01110 - MAIN_PLL16_HSDIV0_CLKOUT 5'b01111 - MAIN_PLL17_HSDIV0_CLKOUT 5'b10000 - MAIN_SYSCLK0 5'b10001 - DEVICE_CLKOUT_32K Reset Source: mod_por_rst_n |