SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
Commands arriving to the DDRSS0 carry the VBUSM priority whereas the DDR controller uses AXI priority. The VBUSM2AXI bridge has the following registers for flexible mapping of the VBUSM priority to DDR controllers's priority:
This allows the system to essentially create different classes of service based on the initiator (Route ID) and the priority of the commands.
The priority map registers map the incoming priority to appropriate priority for the DDR controller as shown in Figure 9-2.
For information about Route ID, see Route ID in System Interconnect.