| 0h |
32 |
A53_WS_BW_LIMITER_REGS_PID |
3040 2000h |
| 4h |
32 |
A53_WS_BW_LIMITER_REGS_CTRL |
3040 2004h |
| 200h |
32 |
A53_WS_BW_LIMITER_REGS_WR_BW_CIR |
3040 2200h |
| 204h |
32 |
A53_WS_BW_LIMITER_REGS_WR_BW_PIR |
3040 2204h |
| 208h |
32 |
A53_WS_BW_LIMITER_REGS_WR_BW_BURST_OFFSET |
3040 2208h |
| 20Ch |
32 |
A53_WS_BW_LIMITER_REGS_WR_BW_INFO |
3040 220Ch |
| 220h |
32 |
A53_WS_BW_LIMITER_REGS_WR_BW_STATS |
3040 2220h |
| 224h |
32 |
A53_WS_BW_LIMITER_REGS_WR_BW_STATS_THRSHLD |
3040 2224h |
| 228h |
32 |
A53_WS_BW_LIMITER_REGS_WR_BW_WINDOWS_CNT |
3040 2228h |
| 22Ch |
32 |
A53_WS_BW_LIMITER_REGS_WR_BW_STATS_CIR |
3040 222Ch |
| 230h |
32 |
A53_WS_BW_LIMITER_REGS_WR_BW_STATS_PIR |
3040 2230h |
| 234h |
32 |
A53_WS_BW_LIMITER_REGS_WR_BW_THRSHLD_CNT |
3040 2234h |
| 238h |
32 |
A53_WS_BW_LIMITER_REGS_WR_BYTES_MAX |
3040 2238h |
| 400h |
32 |
A53_WS_BW_LIMITER_REGS_WR_TXN |
3040 2400h |
| 40Ch |
32 |
A53_WS_BW_LIMITER_REGS_WR_TXN_INFO |
3040 240Ch |
| 420h |
32 |
A53_WS_BW_LIMITER_REGS_WR_TXN_STATS |
3040 2420h |
| 424h |
32 |
A53_WS_BW_LIMITER_REGS_WR_TXN_STATS_THRSHLD |
3040 2424h |
| 428h |
32 |
A53_WS_BW_LIMITER_REGS_WR_TXN_WINDOWS_CNT |
3040 2428h |
| 42Ch |
32 |
A53_WS_BW_LIMITER_REGS_WR_TXN_LIMIT_CNT |
3040 242Ch |
| 430h |
32 |
A53_WS_BW_LIMITER_REGS_WR_TXN_THRESHOLD_CNT |
3040 2430h |
| 434h |
32 |
A53_WS_BW_LIMITER_REGS_WR_TXN_LIMIT_TOTAL |
3040 2434h |
| 438h |
32 |
A53_WS_BW_LIMITER_REGS_WR_TXN_THRESHOLD_TOTAL |
3040 2438h |
| 43Ch |
32 |
A53_WS_BW_LIMITER_REGS_WR_TXN_MAX |
3040 243Ch |