SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
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| Instance Name | Physical Address |
|---|---|
| DDR16SS0 | 0F30 A470h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PI_VREF_VAL_DEV1_1 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PI_VREF_VAL_DEV1_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_VREF_VAL_DEV0_1 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PI_VREF_VAL_DEV0_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED | NONE | 0h | Reserved |
| 30:24 | PI_VREF_VAL_DEV1_1 | R/W | 0h | Defines the range and value for VREF training for DRAM 1 for CS 1. If the PI_VREF_PDA_EN parameter is not set, device 0 values are used for all devices. Reset Source: ctl_amod_g_rst_n |
| 23 | RESERVED | NONE | 0h | Reserved |
| 22:16 | PI_VREF_VAL_DEV1_0 | R/W | 0h | Defines the range and value for VREF training for DRAM 1 for CS 0. If the PI_VREF_PDA_EN parameter is not set, device 0 values are used for all devices. Reset Source: ctl_amod_g_rst_n |
| 15 | RESERVED | NONE | 0h | Reserved |
| 14:8 | PI_VREF_VAL_DEV0_1 | R/W | 0h | Defines the range and value for VREF training for DRAM 0 for CS 1. If the PI_VREF_PDA_EN parameter is not set, device 0 values are used for all devices. Reset Source: ctl_amod_g_rst_n |
| 7 | RESERVED | NONE | 0h | Reserved |
| 6:0 | PI_VREF_VAL_DEV0_0 | R/W | 0h | Defines the range and value for VREF training for DRAM 0 for CS 0. If the PI_VREF_PDA_EN parameter is not set, device 0 values are used for all devices. Reset Source: ctl_amod_g_rst_n |