SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
In general, a single end point has a unique address assignment in the common SoC memory map. However, there are some exceptions.
The I/D RAM for HSM M4F has two sets of the SoC level address assignments shown in Table 2-7. The purpose of this SoC level address aliasing is to provide a single continuous memory view for TIFS core, if the TIFS code is more than 276KB by utilizing the HSM’s I/D RAM.
| Memory End Points | Size | SoC address | Aliased address in the common 36b SoC address map |
|---|---|---|---|
| hsm_sram0_0 | 128K | 0x43C0_0000 | 0x4408_0000 |
| hsm_sram0_1 | 32K | 0x43C2_0000 | 0x440A_0000 |
| hsm_sram0_2 | 16K | 0x43C2_8000 | 0x440A_8000 |
| hsm_sram0_3 | 16K | 0x43C2_c000 | 0x4406_c000 |
| hsm_sram1 | 64K | 0x43C3_0000 | 0x4407_0000 |